Scribe seals and methods of making

Patent metadata

Field	Value
Publication number	US-11069627-B2
Application number	US-201514854896-A
Country	US
Kind code	B2
Filing date	Sep 15, 2015
Priority date	Nov 6, 2014
Publication date	Jul 20, 2021
Grant date	Jul 20, 2021

Abstract

A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

First claim

What is claimed is:

1. A semiconductor die, comprising:
a plurality of layers including a first layer, the first layer having a top surface;
a scribe seal formed in at least one layer of the plurality of layers, the scribe seal including a metal stack having a first metal layer, located proximate the top surface of the first layer; and
a trench that is entirely filled with a sealant formed in at least one layer of the plurality of layers, the trench extending below a plane corresponding to a top surface of the first metal layer and the trench laterally separated from the first metal layer.

2. The semiconductor die of claim 1 ; further comprising:
an electrical insulating layer formed on the top surface of the first layer, the electrical insulating layer covering at least a portion of the top surface of the first layer adjacent the first metal layer and extending a distance laterally from a location of the first metal layer.

3. The semiconductor die of claim 2 , wherein the electrical insulating layer covers the top surface of the first metal layer.

4. The semiconductor die of claim 2 , wherein the electrical insulating layer is at least partially located between the trench and the metal stack.

5. The semiconductor die of claim 2 , wherein the metal stack is a first metal stack and wherein the scribe seal further comprises a second metal stack, wherein the trench is located between the first metal stack and the second metal stack.

6. The semiconductor die of claim 5 , wherein the electrical insulating layer is at least partially located between the second metal stack and the trench.

7. The semiconductor die of claim 5 , wherein the second metal stack has a surface located proximate the top surface of the first layer and wherein the electrical insulating layer covers the surface of the second metal stack.

8. The semiconductor die of claim 5 , wherein the trench extends into the plurality of layers beneath a plane corresponding to a bottom surface of a first metal layer in the second metal stack.

9. The semiconductor die of claim 5 , wherein the second metal stack includes a plurality of metal layers and wherein the plurality of metal layers are electrically connected to each other.

10. The semiconductor die of claim 9 , wherein the plurality of metal layers of the second metal stack are electrically coupled to the first metal layer in the first metal stack.

11. The semiconductor die of claim 5 , wherein the second metal stack circumscribes the semiconductor die.

12. The semiconductor die of claim 1 , wherein the semiconductor die has an edge and wherein the metal stack is located between the edge and the trench.

13. The semiconductor die of claim 1 , wherein the trench extends into the plurality of layers beneath a plane corresponding to a bottom surface of the first metal layer.

14. The semiconductor die of claim 1 , wherein the metal stack includes a plurality of metal layers and wherein the plurality of metal layers are electrically connected to each other.

15. The semiconductor die of claim 14 , wherein the plurality of metal layers are electrically coupled to a ground node.

16. The semiconductor die of claim 1 , wherein the metal stack circumscribes the semiconductor die.

17. A semiconductor die, comprising:
a plurality of layers including a first layer, the first layer having a top surface;
a scribe seal formed in at least one layer of the plurality of layers, the scribe seal including:
a first metal stack having a first metal layer located proximate the top surface of the first layer; and
a second metal stack having a second metal layer located proximate the top surface of the first layer; and

a trench that is entirely filled with a sealant formed in at least one layer of the plurality of layers, the trench formed between a top surface of the first metal stack and a top surface of the second metal stack, and a bottom of the trench in direct contact with an inter-layer dielectric.

18. The semiconductor die of claim 17 ; further comprising an electrical insulating layer formed on the top surface of the first layer, the electrical insulating layer covering at least a portion of the top surface of the first layer adjacent the first metal layer and the second metal layer, wherein the insulating layer extends a distance laterally from a location of the first metal layer and a location of the second metal layer.

19. The semiconductor die of claim 17 , wherein the trench extends below a plane corresponding to a top surface of the first metal layer of the first metal stack.

20. A semiconductor die, comprising:
a plurality of layers including a first layer, the first layer having a top surface;
a scribe seal formed in at least one layer of the plurality of layers, the scribe seal including:
a first metal stack having a first metal layer located proximate the top surface of the first layer;
a second metal stack having a second metal layer located proximate the top surface of the first layer; and
a trench that is entirely filled with a sealant formed in at least one layer of the plurality of layers, the trench extending below a plane corresponding to a top surface of the first metal layer of the first metal stack and the trench laterally separated from the first metal layer.

Assignees

• Texas Instruments Inc

Inventors

• Bonifield Thomas D
• West Jeffrey A
• Williams Byron
• Guo Honglin

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title