Methods and apparatus for high voltage integrated circuit capacitors

Patent metadata

Field	Value
Publication number	US-10847605-B2
Application number	US-201715646465-A
Country	US
Kind code	B2
Filing date	Jul 11, 2017
Priority date	Nov 6, 2014
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

First claim

What is claimed is:

1. A capacitor structure, comprising:
a semiconductor substrate;
a bottom plate comprising a conductive layer over the semiconductor substrate;
a capacitor dielectric layer deposited over at least a portion of the bottom plate and having a first thickness in a first region;
a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and
a top plate conductor formed over a portion but not all of the capacitor dielectric layer in the first region.

2. The capacitor structure of claim 1 , wherein the capacitor dielectric layer is an oxide, and comprising at least one layer of dielectric material formed between the capacitor dielectric layer and the bottom plate that further comprises at least one of silicon nitride and silicon oxynitride.

3. The capacitor structure of claim 2 , wherein the capacitor dielectric layer is a monolithic layer.

4. The capacitor structure of claim 3 , wherein the capacitor dielectric layer comprises an oxide.

5. The capacitor structure of claim 2 , wherein the capacitor dielectric layer comprises multiple dielectric layers.

6. The capacitor structure of claim 2 , wherein the capacitor dielectric layer comprises multiple dielectric layers formed as alternating compressive stress and tensile stress layers.

7. The capacitor structure of claim 2 , wherein a sum of the thicknesses of the capacitor dielectric layer and the at least one layer of dielectric is greater than about 8 ums.

8. The capacitor structure of claim 1 , wherein the first thickness is between 6 ums and 15 ums.

9. A capacitor structure, comprising:
a semiconductor substrate;
a bottom plate comprising a conductive layer over the semiconductor substrate;
a capacitor dielectric layer deposited over at least a portion of the bottom plate and having a first thickness in a first region;
a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and
a top plate conductor formed over at least a portion of the capacitor dielectric layer in the first region, wherein the capacitor dielectric layer further comprises an upper layer comprising silicon dioxide and silicon oxynitride formed between the capacitor dielectric layer and the top plate conductor.

10. The capacitor structure of claim 9 , wherein the upper layer of the capacitor dielectric layer further comprises openings made in the upper layer.

11. The capacitor structure of claim 9 , wherein the capacitor dielectric layer is an oxide, and comprising at least one layer of dielectric material formed between the capacitor dielectric layer and the bottom plate that further comprises at least one of silicon nitride and silicon oxynitride.

12. The capacitor structure of claim 9 , wherein the capacitor dielectric layer comprises an oxide.

13. The capacitor structure of claim 9 , wherein the capacitor dielectric layer comprises multiple dielectric layers.

14. The capacitor structure of claim 9 , wherein the capacitor dielectric layer comprises multiple dielectric layers formed as alternating compressive stress and tensile stress layers.

15. A high voltage capacitor structure, comprising:
a semiconductor substrate;
a bottom plate comprising a metal layer over the semiconductor substrate;
a capacitor dielectric layer deposited over at least a portion of the bottom plate and having a first thickness between 6 um and 20 um in a first region;
a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and
a top plate comprising metal formed over only a portion of the capacitor dielectric layer in the first region.

16. The high voltage capacitor structure of claim 15 , wherein the capacitor dielectric layer is an oxide, and comprising at least one layer of dielectric material formed between the capacitor dielectric layer and the bottom plate that further comprises at least one of silicon nitride and silicon oxynitride.

17. The high voltage capacitor structure of claim 15 , wherein the capacitor dielectric layer is a monolithic layer.

18. The high voltage capacitor structure of claim 15 , wherein the capacitor dielectric layer comprises an oxide.

19. The high voltage capacitor structure of claim 15 , wherein the capacitor dielectric layer comprises multiple dielectric layers.

20. The high voltage capacitor structure of claim 15 , wherein the capacitor dielectric layer comprises multiple dielectric layers formed as alternating compressive stress and tensile stress layers.

Assignees

• Texas Instruments Inc

Inventors

• West Jeffrey Alan
• Bonifield Thomas D
• Williams Byron Lovell

Classifications

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title