Hybrid isolation capacitors in series

Patent metadata

Field	Value
Publication number	US-12490443-B2
Application number	US-202117512194-A
Country	US
Kind code	B2
Filing date	Oct 27, 2021
Priority date	Oct 27, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

An integrated circuit includes a first isolation capacitor and a second isolation capacitor. The first isolation capacitor is electrically connected to a first circuit node and has first and second capacitor plates separated by a first dielectric stack. The second isolation capacitor is electrically connected in series between the first isolation capacitor and a second circuit node, and includes third and fourth capacitor plates separated by a second dielectric stack different from the first dielectric stack.

First claim

What is claimed is:

1 . A method of forming an integrated circuit, comprising:
attaching a first isolation capacitor to a package substrate, the first isolation capacitor having first and second capacitor plates separated by a first dielectric stack including a first dielectric material composition; attaching a second isolation capacitor to the package substrate, the second isolation capacitor having third and fourth capacitor plates separated by a second dielectric stack including a different second dielectric material composition; electrically connecting the first capacitor plate of the first isolation capacitor to the third capacitor plate of the second isolation capacitor; electrically connecting the second plate of the first isolation capacitor to a first package node; and electrically connecting the fourth plate of the second isolation capacitor to a second package node.

2 . The method of claim 1 , wherein the first dielectric stack includes only silicon-based dielectric materials, and the second dielectric stack includes an organic dielectric material.

3 . The method of claim 2 , wherein the second dielectric stack includes a polyimide layer between the third and fourth capacitor plates.

4 . The method of claim 1 , wherein the first and second isolation capacitors are mounted on a same package substrate, and are connected in series between a first package node and a second package node.

5 . The method of claim 1 , wherein the second dielectric stack includes an organic material and the second isolation capacitor includes an aluminum oxide layer over the organic material.

6 . The method of claim 1 , wherein the second dielectric stack includes a polymer dielectric layer having a thickness of about 30 μm.

7 . The method of claim 1 , wherein the first dielectric stack includes 15.6 μm of silicon-based dielectric materials, and the second dielectric stack includes about 30 μm of polyimide.

8 . The method of claim 1 , wherein a ramp to breakdown between the first and second package nodes is greater than 18 kV rms .

9 . The method of claim 1 , wherein a surge capacity between the first and the second package nodes is at least 22 kV rms .

10 . The method of claim 1 , wherein the first and second isolation capacitors are mounted to a lead frame and packaged within a mold compound.

11 . A method of forming an integrated circuit, comprising:
attaching a first isolation capacitor to a package substrate, the first isolation capacitor having first and second capacitor plates separated by a first dielectric stack including a first dielectric material; attaching a second isolation capacitor to the package substrate, the second isolation capacitor having third and fourth capacitor plates separated by a second dielectric stack that excludes the first dielectric material; electrically connecting the first capacitor plate of the first isolation capacitor to the third capacitor plate of the second isolation capacitor; electrically connecting the second plate of the first isolation capacitor to a first circuit node; and electrically connecting the fourth plate of the second isolation capacitor to a second circuit node.

12 . The method of claim 11 , wherein the first dielectric material includes an organic dielectric material.

13 . The method of claim 11 , wherein the first dielectric material includes a polyimide material.

14 . The method of claim 11 , wherein the first and second isolation capacitors are mounted on a same package substrate, and are connected in series between a first package node and a second package node.

15 . The method of claim 11 , wherein the second dielectric stack includes an organic material and the second isolation capacitor includes an aluminum oxide layer over the organic material.

16 . The method of claim 11 , wherein the first dielectric stack includes 15.6 μm of silicon-based dielectric materials, and the second dielectric stack includes about 30 μm of polyimide.

17 . The method of claim 11 , wherein a ramp to breakdown between the first and second circuit nodes is greater than 18 kV rms .

18 . The method of claim 11 , wherein a surge capacity between the first and the second circuit nodes is at least 22 kV rms .

19 . The method of claim 11 , wherein the first and second isolation capacitors are mounted to a lead frame and packaged within a mold compound.

20 . A method of forming a packaged integrated circuit device, comprising:
attaching a first isolation capacitor to a package substrate, the first isolation capacitor having first and second capacitor plates separated by a first dielectric stack including a polyimide material; attaching a second isolation capacitor to the package substrate, the second isolation capacitor having third and fourth capacitor plates separated by a second dielectric stack that includes only one or more inorganic dielectric materials; forming a wirebond connection between the first capacitor plate of the first isolation capacitor and the third capacitor plate of the second isolation capacitor; forming a wire bond connection between the second plate of the first isolation capacitor and a first package node; and forming a wire bond connection between the fourth plate of the second isolation capacitor to a second package node.

Assignees

• Texas Instruments Inc

Inventors

• Guo Honglin
• Bonifield Thomas D

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title