Flash memory having water vapor induced air gaps and fabricating method thereof
US-10418370-B2 · Sep 17, 2019 · US
with an inter-gate dielectric layer also being used as part of the peripheral transistor
with an inter-gate dielectric layer also being used as part of the peripheral transistor · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B41/46 |
| Official title | with an inter-gate dielectric layer also being used as part of the peripheral transistor |
| Display label | with an inter-gate dielectric layer also being used as part of the peripheral transistor |
| Total patents | 163 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 9 |
| 2016 | 13 |
| 2017 | 23 |
| 2018 | 14 |
| 2019 | 11 |
| 2020 | 6 |
| 2021 | 27 |
| 2022 | 26 |
| 2023 | 17 |
| 2024 | 11 |
| 2025 | 3 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method for manufacturing semiconductor memory device
US-2018342527-A1 · Nov 29, 2018 · US
Electronic chip manufacturing method
US-2018286878-A1 · Oct 4, 2018 · US
Non-volatile memory having individually optimized silicide contacts and process therefor
US-10056262-B2 · Aug 21, 2018 · US
Semiconductor device manufacturing method including implementing elements of memory unit and logic unit
US-10014307-B2 · Jul 3, 2018 · US
Electronic chip manufacturing method
US-10014308-B2 · Jul 3, 2018 · US
Integration of floating gate memory and logic device in replacement gate flow
US-2018166456-A1 · Jun 14, 2018 · US
Semiconductor device and manufacturing method thereof
US-2018151582-A1 · May 31, 2018 · US
Semiconductor device and method of fabricating semiconductor device
US-9978762-B2 · May 22, 2018 · US
Method of forming low height split gate memory cells
US-9972493-B2 · May 15, 2018 · US
Marked pixel unit, display device using the same, and method for fabricating the display device
US-2018061709-A1 · Mar 1, 2018 · US
Integration of floating gate memory and logic device in replacement gate flow
US-2018053773-A1 · Feb 22, 2018 · US
Integration of floating gate memory and logic device in replacement gate flow
US-9899397-B1 · Feb 20, 2018 · US
Method Of Forming Low Height Split Gate Memory Cells
US-2018040482-A1 · Feb 8, 2018 · US
Memory device
US-2018005835-A1 · Jan 4, 2018 · US
Method of forming a semiconductor device structure and semiconductor device structure
US-9842845-B1 · Dec 12, 2017 · US
Nonvolatile semiconductor memory device and method of manufacturing the same
US-9837264-B2 · Dec 5, 2017 · US
Semiconductor device and method of forming the same
US-9812327-B2 · Nov 7, 2017 · US
Nonvolatile memory device and method for manufacturing the same
US-2017221914-A1 · Aug 3, 2017 · US
Semiconductor device and method of fabricating semiconductor device
US-2017221913-A1 · Aug 3, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B41/46?
- CPC H10B41/46 is the Cooperative Patent Classification code for “with an inter-gate dielectric layer also being used as part of the peripheral transistor.”
- How many patents are filed under CPC H10B41/46 (with an inter-gate dielectric layer also being used as part of the peripheral transistor)?
- Our database includes 163 publications tagged with this CPC code.
- Is patent activity under CPC H10B41/46 growing?
- Publication counts under this code: 11 in 2024 vs 3 in 2025 (latest complete years).