Non-volatile memory having individually optimized silicide contacts and process therefor

Patent metadata

Field	Value
Publication number	US-10056262-B2
Application number	US-201715479508-A
Country	US
Kind code	B2
Filing date	Apr 5, 2017
Priority date	Jan 9, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

First claim

It is claimed:

1. A method of forming a memory, comprising:
forming a multi-layer slab on top of a semiconductor substrate with layers corresponding to structures of an array of NAND strings, and wherein the layers include a first region for forming memory cells of the NAND strings and a second region for forming select transistors and peripheral circuits components, and wherein a first polysilicon layer is deposited as a top layer of the multi-layer slab;
masking the first polysilicon layer with a mask layer that leaves unmasked areas in designated areas among the second region;
etching trenches in the unmasked areas;
depositing a second polysilicon layer in the trenches;
etching back the second polysilicon layer to the mask layer;
depositing a first metal layer;
annealing to form a first silicide layer between the first metal layer and the second polysilicon layer interfacing with the first metal layer;
removing the first metal layer;
removing the mask layer to expose the first polysilicon layer;
depositing a second metal layer; and
annealing to form a second silicide layer between the second metal layer and the first polysilicon layer.

2. The method as in claim 1 , wherein:
the peripheral circuits components include slit contacts;
said etching back the second polysilicon layer to the mask layer also creates at each slit contact an exposed portion of a floating gate polysilicon below the first polysilicon layer; and
said annealing to form a first silicide layer between the first metal layer and the second polysilicon layer interfacing with the first metal layer also has the first silicide layer formed between the first metal layer and the exposed floating gate polysilicon.

3. The method as in claim 1 , wherein:
the first and second metal layers are tungsten.

4. The method as in claim 1 , wherein:
the first polysilicon layer is for forming a portion of control gates of the memory cells.

5. The method as in claim 1 , wherein:
the first polysilicon layer is doped.

6. The method as in claim 1 , wherein:
the second polysilicon layer is for forming poly plugs that connect between the first polysilicon layer and a floating gate polysilicon layer.

7. A method of forming a memory having memory cells arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions, said method comprising:
forming a multi-layer slab on top of a semiconductor substrate in an x-y plane, the layers of the multi-layer slab being stacked in the z-direction and corresponding to structures of an array in the x-y plane of NAND strings, and wherein the layers include a first region for forming memory cells of the NAND strings and a second region for forming select transistors and peripheral circuits components, and wherein a first polysilicon layer is deposited as a top layer of the multi-layer slab;
masking the first polysilicon layer with a mask layer that leaves unmasked areas in designated areas among the second region;
etching trenches in the unmasked areas;
depositing a second polysilicon layer in the trenches;
etching back the second polysilicon layer to the mask layer;
depositing a first metal layer;
annealing to form a first silicide layer between the first metal layer and the second polysilicon layer interfacing with the first metal layer;
removing the first metal layer;
removing the mask layer to expose the first polysilicon layer;
depositing a second metal layer; and
annealing to form a second silicide layer between the second metal layer and the first polysilicon layer.

8. The method as in claim 7 , wherein:
the peripheral circuits components include slit contacts;
said etching back the second polysilicon layer to the mask layer also creates at each slit contact an exposed portion of a floating gate polysilicon below the first polysilicon layer; and
said annealing to form a first silicide layer between the first metal layer and the second polysilicon layer interfacing with the first metal layer also has the first silicide layer formed between the first metal layer and the exposed floating gate polysilicon.

9. The method as in claim 7 , wherein:
the first and second metal layers are tungsten.

10. The method as in claim 7 , wherein:
the first polysilicon layer is for forming a portion of control gates of the memory cells.

11. The method as in claim 7 , wherein:
the second polysilicon layer is for forming poly plugs that connect between the first polysilicon layer and a floating gate polysilicon layer.

Assignees

• Sandisk Technologies Llc

Inventors

• Tsukamoto Keisuke

Classifications

• H10D64/0131 Primary

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H01L27/11529

  Electricity · mapped topic

• H01L21/28052 Primary

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L27/11526

  Electricity · mapped topic