Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-9812327-B2
Application number	US-201514863177-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Aug 24, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a cell area and a MOS device area;
a first gate, buried in an opening of the substrate in the cell area;
a second gate, disposed on the substrate in the cell area, wherein the second gate comprises metal;
an inter-gate dielectric layer, disposed between the first gate and the second gate; and
a third gate, disposed on the substrate in the MOS device area, wherein the third gate comprises metal,
wherein the inter-gate dielectric layer is in physical contact with an upper sidewall of the opening and further extends to directly cover a top corner of the opening, and
wherein an upper surface of the second gate and an upper surface of the third gate are coplanar and a bottom surface of the second gate and a bottom surface of the third gate are coplanar.

2. The semiconductor device of claim 1 , wherein a dimension of the second gate is greater than a dimension of the first gate, and the inter-gate dielectric layer is further disposed between the second gate and the substrate.

3. The semiconductor device of claim 1 , wherein the inter-gate dielectric layer comprises an oxide-nitride-oxide (ONO) dielectric layer, a high-dielectric-constant (high-k) layer having a dielectric constant of greater than about 10 or a combination thereof.

4. The semiconductor device of claim 3 , wherein the high-k layer comprises metal oxide.

5. The semiconductor device of claim 1 , further comprising a tunnel insulating layer disposed between the first gate and the substrate.

6. The semiconductor device of claim 1 , further comprising at least two doped regions disposed in the substrate beside the first gate.

7. The semiconductor device of claim 6 , wherein a depth of the first gate is greater than a depth of the doped regions.

8. A method of forming a semiconductor device, comprising:
providing a substrate having a cell area and a MOS device area, wherein the substrate has at least one opening formed in the cell area;
forming an insulating layer on a surface of the opening;
filling a first conductive layer in the opening to form a first gate; and
forming a first dielectric layer and a second conductive layer on the first conductive layer in the cell area and forming a third conductive layer on the substrate in the MOS device area, and
replacing each of the second conductive layer and the third conductive layer with a second gate and a third gate, respectively, wherein the second gate and the third gate comprise a metal gate, respectively,
wherein the first dielectric layer is in physical contact with an upper sidewall of the opening and further extends to directly cover a top corner of the opening, and
wherein an upper surface of the second gate and an upper surface of the third gate are coplanar and a bottom surface of the second gate and a bottom surface of the third gate are coplanar.

9. The method of claim 8 , wherein the step of replacing each of the second conductive layer and the third conductive layer with a second gate and a third gate comprises:
forming a second dielectric layer around the second conductive layer and the third conductive layer;
removing the second conductive layer and the third conductive layer to form trenches in the second dielectric layer; and
filling a metal layer in the trenches.

10. The method of claim 9 , wherein the second conductive layer and the third conductive layer comprise polysilicon, amorphous silicon or a combination thereof.

11. The method of claim 8 , wherein the first dielectric layer comprises an ONO dielectric layer, a high-k layer having a dielectric constant greater than about 10 or a combination thereof.

12. The method of claim 8 , wherein a surface of the first conductive layer is lower than a surface of the substrate.

13. The method of claim 8 , wherein the first dielectric layer in the cell and a high-k layer below a metal gate in the MOS device area are formed simultaneously.

Assignees

• United Microelectronics Corp

Inventors

• Yu Kun-Huang
• Hsiao Shih-Yin

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L27/11536

  Electricity · mapped topic

• H01L21/28273 Primary

  Electricity · mapped topic

• H01L29/42336

  Electricity · mapped topic

• H01L27/11539

  Electricity · mapped topic