Semiconductor device and method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-9978762-B2
Application number	US-201715487419-A
Country	US
Kind code	B2
Filing date	Apr 13, 2017
Priority date	Sep 17, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
providing a substrate with a memory region and a logic region;
forming a recess of the substrate in the memory region;
forming a non-volatile gate stack in the recess, wherein the non-volatile gate stack is composed of a first polysilicon layer and a second polysilicon layer; and
forming a logic gate stack in the logic region after forming the non-volatile gate stack, wherein the logic gate stack is composed of a third polysilicon layer, and a top surface of the third polysilicon layer is higher than a top surface of the second polysilicon layer.

2. The method of fabricating the semiconductor device according to claim 1 , wherein the step of forming the non-volatile gate stack comprises:
forming the first polysilicon layer on a top surface of the substrate to fill the recess;
removing a portion of the first polysilicon layer higher than the top surface of the substrate;
forming at least two memory STI trenches in the memory region and removing a portion of the first polysilicon layer in the memory region simultaneously, wherein a remained portion of the first polysilicon layer disposed between the two memory STI trenches forms a floating gate;
filling the memory STI trenches with an isolation layer to form memory STI structures;
forming a dielectric layer and the second polysilicon layer on the floating gate in order; and
removing a portion of the second polysilicon layer to form a control gate on the floating gate.

3. The method of fabricating the semiconductor device according to claim 2 , wherein the step of forming the non-volatile gate stack further comprises etching back the memory STI structures such that a top surface of the memory STI structures is lower than the top surface of the substrate.

4. The method of fabricating the semiconductor device according to claim 2 , wherein a depth of the recess is about 500 to about 2500 angstroms, and a thickness of the first polysilicon layer is about 500 to about 2500 angstroms.

5. The method of fabricating the semiconductor device according to claim 1 , further comprising forming a buffer layer to cover the non-volatile gate stack before forming the logic gate stack.

6. The method of fabricating the semiconductor device according to claim 1 , wherein the logic gate stack has a first top surface, the non-volatile gate stack has a second top surface, and the second top surface is lower than the first top surface by a step height.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Ching
• Chen Ko-Chi
• Wang Shen-De

Classifications

• H01L27/11529 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11531

  Electricity · mapped topic

• H10B41/44

  with a control gate layer also being used as part of the peripheral transistor · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title