Integration of floating gate memory and logic device in replacement gate flow

Patent metadata

Field	Value
Publication number	US-9899397-B1
Application number	US-201615241759-A
Country	US
Kind code	B1
Filing date	Aug 19, 2016
Priority date	Aug 19, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a logic transistor located in a logic device region of a substrate, the logic transistor comprising:
a first functional gate stack contacting a first body region of a first semiconductor fin and including a first high-k gate dielectric and a first gate electrode surrounded by the first high-k gate dielectric, and
first source/drain regions located within the first semiconductor fin and laterally surrounding the first body region; and

a non-volatile memory transistor located in a memory device region of the substrate, the non-volatile memory transistor comprising:
a second functional gate stack contacting a second body region of a second semiconductor fin and including a tunnel oxide portion, a floating gate electrode, a control oxide portion, a second high-k gate dielectric and a second gate electrode surrounded by the second high-k gate dielectric, and
second source/drain regions located within the second semiconductor fin and laterally surrounding the second body region,

wherein each of the first high-k gate dielectric and the second high-k gate dielectric is a U-shaped gate dielectric, wherein a horizontal portion of the first high-k gate dielectric is in direct contact with the first body region of the first semiconductor fin, and a horizontal portion of the second high-k dielectric is in direct contact with the control oxide portion.

2. The semiconductor structure of claim 1 , wherein the logic transistor further comprises a first gate spacer located on sidewalls of the first gate stack, wherein vertical portions of the first high-k gate dielectric are in contact with the first gate spacer.

3. The semiconductor structure of claim 1 , wherein the non-volatile memory transistor further comprises a second gate spacer located on sidewalls of the second gate stack, wherein sidewalls of the tunneling oxide portion, the floating gate electrode and the control oxide portion are in contact with lower portions of the second gate spacer, and vertical portions of the second high-k gate dielectric are in contact with upper portions of the second gate spacer.

4. The semiconductor structure of claim 1 , further comprising an interlevel dielectric (ILD) layer laterally surrounding the first gate stack and the second gate stack.

5. The semiconductor structure of claim 4 , further comprising first source/drain contact structures extending through the ILD layer and contacting the first source/drain regions, and second source/drain contact structures extending through the ILD layer and contacting the second source/drain regions.

6. The semiconductor structure of claim 4 , further comprising a shallow trench isolation (STI) layer laterally surrounding a lower portion of each of the first semiconductor fin and the second semiconductor fin, wherein the ILD layer contacts a top surface of the STI layer.

7. The semiconductor structure of claim 1 , wherein the first gate stack further comprises a first work function material portion located between the first high-k gate dielectric and the first gate electrode, and the second gate stack further comprises a second work function material portion located between the second high-k gate dielectric and the second gate electrode.

8. The semiconductor structure of claim 1 , wherein each of the tunneling oxide portion and the control oxide portion comprises silicon dioxide, and the floating gate electrode comprises polysilicon.

9. A method of forming a semiconductor structure comprising:
forming a first sacrificial gate stack over a first body region of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a second body region of a second semiconductor fin located in a memory device region of the substrate, wherein the first sacrificial gate stack comprises a first tunneling oxide portion, a first floating gate electrode, a first control oxide portion, a first gate conductor and a first gate cap, and the second sacrificial gate stack comprises a second tunneling oxide portion, a second floating gate electrode, a second control oxide portion, a second gate conductor and a second gate cap;
forming a first gate cavity by removing an entirety of the first sacrificial gate stack and a second gate cavity by removing the second gate cap and the second gate conductor in the second sacrificial gate stack; and
forming a first high-k gate dielectric over a bottom surface and sidewalls of the first gate cavity and a first gate electrode filling a remaining volume of the first gate cavity, and a second high-k gate dielectric over a bottom surface and sidewalls of the second gate cavity and a second gate electrode filling a remaining volume of the second gate cavity.

10. The method of claim 9 , wherein the first gate cavity exposes the first body region of the first semiconductor fin, and the second gate cavity exposes the second control oxide portion in the second sacrificial gate stack.

11. The method of claim 9 , wherein the forming the first gate cavity and the second gate cavity comprises:
removing the first gate cap and the first gate conductor in the first sacrificial gate stack and the second gate cap and the second gate conductor in the second sacrificial gate stack;
forming a patterned mask layer to cover the memory device region while exposing the logic device region, wherein the patterned mask layer covers remaining components of the second sacrificial gate stack, but not remaining components of the first sacrificial gate stack;
removing the remaining components of the first sacrificial gate stack including the first control oxide portion, the first floating gate electrode and the first tunneling oxide portion from the logic device region to expose the first body region of the first semiconductor fin; and
removing the patterned mask layer.

12. The method of claim 9 , further comprising forming a first gate spacer on sidewalls of the first sacrificial gate stack, and forming a second gate spacer on sidewalls of the second sacrificial gate stack.

13. The method of claim 12 , further comprising forming first source/drain regions within portions of the first semiconductor fin that do not underlie the first sacrificial gate stack, and second source/drain regions within portions of the second semiconductor fin that do not underlie the second sacrificial gate stack, wherein the first source/drain region laterally surround the first body region, and the second source/drain region laterally surround the second body region.

14. The method of claim 13 , wherein the forming the first source/drain regions and the second source/drain regions is performed by an ion implantation.

15. The method of claim 13 , further comprising forming an interlevel dielectric (ILD) layer over the substrate, the ILD layer laterally surrounding the first gate spacer and the second gate spacer.

16. The method of claim 15 , further comprising forming a shallow trench isolation (STI) layer around a lower portion of each of the first semiconductor fin and the second semiconductor fin.

17. The method of claim 15 , further comprising forming first source/drain contact structures extending through the ILD layer and contacting the first source/drain regions, and second source/drain contact structures extending through the ILD layer and contacting the second source/drain regions.

18. The method of claim 9 , further comprising forming a first work function material portion between the first high-k gate dielectric and the first gate electrode, and a second wor

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H01L27/11539 Primary

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/11536

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic