Semiconductor device manufacturing method including implementing elements of memory unit and logic unit

Patent metadata

Field	Value
Publication number	US-10014307-B2
Application number	US-201514961525-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Dec 25, 2014
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a first designated region, wherein the first conductor is positioned between the first dielectric and the substrate, wherein the second conductor is positioned between the second dielectric and the substrate, and wherein the first designated region is positioned in the substrate;
providing a conductive material layer, which covers the first dielectric and the second dielectric;
partially removing the conductive material layer to form remaining portions of the conductive material layer, which include a third conductor and a fourth conductor, wherein the first dielectric is positioned between the third conductor and the first conductor, and wherein the fourth conductor directly contacts the first designated region;
implementing a floating gate electrode of a memory unit using the first conductor;
implementing a control gate electrode of the memory unit using the third conductor;
implementing a gate electrode of a first logic unit using the second conductor; and
implementing a source region or a drain region of the first logic unit using the first designated region.

2. The method of claim 1 , comprising:
providing a dielectric material member on a conductive material member; and
partially removing the dielectric material and the conductive material member to form the first dielectric, the second dielectric, the first conductor, and the second conductor.

3. The method of claim 1 , comprising:
removing the second dielectric after both the third conductor and the fourth conductor have been formed.

4. The method of claim 1 , comprising:
using the third conductor and the fourth conductor as parts of a mask in a process of removing the second dielectric; and
removing the second dielectric through a space between the third conductor and the fourth conductor.

5. The method of claim 1 ,
wherein the second dielectric is exposed after the partially removing the conductive material layer, and
wherein the first dielectric remains covered after the partially removing the conductive material layer.

6. The method of claim 1 ,
wherein the first conductor is positioned between the first dielectric and a first doped well of the substrate, and
wherein the second conductor is positioned between the second dielectric and the first doped well of the substrate.

7. The method of claim 1 , comprising:
providing a first spacer, which directly contacts the second conductor and is positioned between the second conductor and the first conductor,
wherein the third conductor directly contacts the first spacer.

8. The method of claim 7 , comprising:
using the third conductor to protect the first spacer when removing the second dielectric.

9. The method of claim 7 , comprising:
providing a second spacer, which directly contacts each of the first conductor and the first dielectric,
wherein the third conductor directly contacts the second spacer.

10. The method of claim 9 , wherein a portion of the third conductor is positioned between a portion of the first spacer and a portion of the second spacer in a direction parallel to a bottom side of the substrate.

11. The method of claim 9 , wherein the first spacer directly contacts the second spacer.

12. The method of claim 1 , comprising:
providing a first spacer, which directly contacts each of the first conductor and the first dielectric and is positioned between the second conductor and the first conductor,
wherein the third conductor directly contacts each of the first spacer and the first dielectric.

13. The method of claim 1 , comprising:
providing a fifth conductor and a third dielectric layer, wherein the fifth conductor is positioned between the third dielectric layer and the substrate;
providing a second designated region, which is positioned in the substrate;
providing an insulator, which is positioned between the first designated region and the second designated region;
implementing a gate electrode of a second logic unit using the fifth conductor; and
implementing a source region or a drain region of the second logic unit using the second designated region,
wherein the fourth conductor directly contacts each of the first designated region and the second designated region.

14. The method of claim 13 , comprising:
providing a first spacer, which directly contacts the second conductor; and
providing a second spacer, which directly contact the fifth conductor,
wherein the fourth conductor directly contacts each of the first spacer and the second spacer.

15. The method of claim 14 , comprising:
using the fourth conductor to protect the first spacer and the second spacer when removing the second dielectric and the third dielectric.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Chan Yipeng
• Dong Jieqiong
• Jin Huajun
• Zhou Ruling
• Guo Shibi
• Kim Bongkil

Classifications

• H01L27/11539

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L29/7881

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/42324

  Electricity · mapped topic