Nonvolatile semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9837264-B2
Application number	US-201615074033-A
Country	US
Kind code	B2
Filing date	Mar 18, 2016
Priority date	Jul 16, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A nonvolatile semiconductor memory device comprises: a substrate; a memory cell that is disposed on the substrate and accumulates a charge as data; and a cover layer covering the memory cell. The cover layer has a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a memory cell side.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a substrate;
a memory cell disposed within a memory cell region on the substrate, the memory cell accumulating a charge as data; and
a cover layer covering the memory cell, the cover layer having a structure in which a first silicon nitride layer, an intermediate layer, and a second silicon nitride layer are stacked sequentially from a side of the memory cell, the intermediate layer being amorphous silicon; wherein
the memory cell comprises: a gate insulating film disposed on the substrate; a floating gate electrode disposed on the gate insulating film; a block insulating film disposed above the floating gate electrode; and a control gate electrode disposed on the block insulating film;
a select transistor is disposed in a periphery of the memory cell within a memory cell region;
a peripheral transistor is disposed within a peripheral region, the peripheral region being in a periphery of the memory cell array region; and a contact is disposed in a periphery of said peripheral transistor;
the cover layer covers an upper portion of the peripheral transistor and has an end of the cover layer contacting the contact;
a spacer configured from an insulator is disposed on the upper portion of the peripheral transistor;
the cover layer is disposed curved toward a substrate surface direction in the portion shifting from the memory cell array region to the peripheral region, so as to cover upper portions of the memory cell and the select transistor and face part of a side surface of the select transistor; and
the cover layer is divided by the spacer.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein
the intermediate layer is silicon oxide.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein
the second silicon nitride layer is thicker than the first silicon nitride layer.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein
the cover layer further comprises: a second intermediate layer disposed on an upper surface of the second silicon nitride layer; and a third silicon nitride layer disposed on an upper surface of said second intermediate layer.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein
an inter-layer insulating layer configured from silicon oxide is interposed between the memory cell and the cover layer.

Assignees

• Toshiba Memory Corp

Inventors

• Shamoto Reiko
• Takekida Hideto

Classifications

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6903

  containing silicon · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title