Excess loop delay estimation and correction
US-2019379390-A1 · Dec 12, 2019 · US
Compensation or reduction of delay or phase error
Compensation or reduction of delay or phase error · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H03M3/37 |
| Official title | {Compensation or reduction of delay or phase error} |
| Display label | Compensation or reduction of delay or phase error |
| Total patents | 119 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 15 |
| 2016 | 15 |
| 2017 | 12 |
| 2018 | 10 |
| 2019 | 13 |
| 2020 | 11 |
| 2021 | 11 |
| 2022 | 11 |
| 2023 | 6 |
| 2024 | 7 |
| 2025 | 5 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Delta-sigma modulator
US-10484004-B2 · Nov 19, 2019 · US
Sigma delta modulator, integrated circuit and method therefor
US-10439633-B2 · Oct 8, 2019 · US
Delta-sigma modulator
US-2019288705-A1 · Sep 19, 2019 · US
Interleaving quantizer in continuous-time delta-sigma modulator for quantization level increment
US-10374626-B2 · Aug 6, 2019 · US
Systems and methods for digital excess loop delay compensation in a continuous time delta sigma modulator
US-2019149164-A1 · May 16, 2019 · US
Continuous-time analog-to-digital converter
US-10277241-B1 · Apr 30, 2019 · US
Continuous-time delta-sigma ADC with scalable sampling rates and excess loop delay compensation
US-10243578-B2 · Mar 26, 2019 · US
Sigma delta modulator, integrated circuit and method therefor
US-2018343013-A1 · Nov 29, 2018 · US
Input path matching in pipelined continuous-time analog-to-digital converters
US-10084473-B2 · Sep 25, 2018 · US
ΔΣ modulator with excess loop delay compensation
US-10075181-B2 · Sep 11, 2018 · US
Sigma delta modulator and signal conversion method thereof
US-10069509-B2 · Sep 4, 2018 · US
Continuous-time delta-sigma adc with scalable sampling rates and excess loop delay compensation
US-2018241409-A1 · Aug 23, 2018 · US
Hybrid second-order noise coupling technique for continuous-time delta-sigma modulators
US-2018219558-A1 · Aug 2, 2018 · US
Circuits and methods for excess loop delay compensatin in delta-sigma modulators
US-2018212618-A1 · Jul 26, 2018 · US
Sigma delta modulator and signal conversion method thereof
US-2018159550-A1 · Jun 7, 2018 · US
Delta-sigma modulator and modulation method, transmission device, and transmission method
US-9887705-B2 · Feb 6, 2018 · US
Analog-to-digital converter with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay compensation
US-9871534-B2 · Jan 16, 2018 · US
Analog-to-digital converter with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay compensation
US-2017353192-A1 · Dec 7, 2017 · US
Delta-sigma modulator and modulation method, transmission device, and transmission method
US-2017331491-A1 · Nov 16, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H03M3/37?
- CPC H03M3/37 is the Cooperative Patent Classification code for “Compensation or reduction of delay or phase error.”
- How many patents are filed under CPC H03M3/37 (Compensation or reduction of delay or phase error)?
- Our database includes 119 publications tagged with this CPC code.
- Is patent activity under CPC H03M3/37 growing?
- Publication counts under this code: 7 in 2024 vs 5 in 2025 (latest complete years).