Input path matching in pipelined continuous-time analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-10084473-B2
Application number	US-201715455971-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	Mar 13, 2015
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

First claim

What is claimed is:

1. An apparatus for use in a pipelined continuous-time analog-to-digital converter (CT ADC), including a plurality of pipelined sub-analog-to-digital converters (sub-ADCs), including at least a first stage sub-ADC and a final stage sub-ADC, the apparatus comprising:
a first pipelined stage, including the first stage sub-ADC, and including
an input delay circuit positioned in a continuous-time signal path of the pipelined CT ADC and coupled to a first summing circuit; and
at least one digital delay circuit coupled to an output of the first stage sub-ADC, the at least one digital delay circuit coupled to each of the first summing circuit and an output summing circuit;

the output summing circuit coupled to the at least one digital delay circuit of the first stage sub-ADC, and an output of the final stage sub-ADC.

2. The apparatus of claim 1 , wherein the input delay circuit is a passive filter network including at least one low-pass filter and at least one all-pass filter, the least one low-pass filter including at least one resistor-capacitor circuit and the at least one all-pass filter including at least one of: at least one resistor-capacitor circuit and at least one resistor-inductor-capacitor circuit.

3. The apparatus of claim 1 , wherein the input delay circuit is at least one of: a digitally controlled delay and a transmission line producing a fixed delay.

4. The apparatus of claim 1 , wherein the at least one digital delay circuit is coupled to the first summing circuit via a sub-digital-to-analog converter, and coupled to the output summing circuit via a digital noise cancellation filter.

5. The apparatus of claim 1 , wherein the pipelined CT ADC is an integrated circuit and is a pipelined continuous-time delta sigma modulator (CT DSM), and the first stage sub-ADC is a first stage sub-delta sigma modulator (sub-DSM) of a plurality of pipelined sub-DSMs.

6. The apparatus of claim 1 , wherein the at least one digital delay circuit comprises two digital delay circuits, the first digital delay circuit coupled to the first summing circuit and the second digital delay circuit coupled to the output summing circuit, the first digital delay circuit having a delay different from a delay of the second digital delay circuit.

7. A pipelined continuous-time analog-to-digital converter (CT ADC) device comprising:
a plurality of pipelined sub-analog-to-digital converters (sub-ADCs), including at least a first stage sub-ADC, and a final stage sub-ADC;
the first stage sub-ADC receiving an analog input signal;
a continuous-time signal path receiving the analog input signal, the continuous-time input path including an input delay circuit positioned before a first summing circuit; and
at least one digital delay circuit coupled to an output of the first stage sub-ADC, the at least one digital delay circuit coupled to each of the first summing circuit and an output summing circuit;
the output summing circuit coupled to the at least one digital delay circuit and an output of the final stage sub-ADC.

8. The device of claim 7 further comprising:
a digital noise cancellation filter coupled to an output of the at least one digital delay circuit;
a sub-digital-to-analog converter (sub-DAC) coupled to an output of the at least one digital delay circuit;
the first summing circuit further coupled to an output of the sub-DAC, the sub-DAC coupled to the output of the first stage sub-ADC; and
the output summing circuit coupled to an output of the digital noise cancellation filter, the digital noise cancellation filter coupled to the at least one digital delay circuit.

9. The device of claim 7 , wherein the input delay circuit is a passive filter network including at least one low-pass filter and at least one all-pass filter, the least one low-pass filter including at least one resistor-capacitor circuit and the at least one all-pass filter including at least one of: at least one resistor-capacitor circuit and at least one resistor-inductor-capacitor circuit.

10. The device of claim 7 , wherein the input delay circuit is at least one of: a digitally controlled delay and a transmission line producing a fixed delay.

11. The device of claim 7 , in which the pipelined CT ADC device is an integrated circuit and a pipelined continuous-time delta sigma modulator (CT DSM) device, and the first stage sub-ADC and the final stage sub-ADC are a first stage sub-delta sigma modulator (sub-DSM) and a second stage sub-DSM of a plurality of pipelined sub-DSMs.

12. The device of claim 7 , wherein the at least one digital delay circuit comprises two digital delay circuits, the first digital delay circuit coupled to the first summing circuit and the second digital delay circuit coupled to the output summing circuit, the first digital delay circuit having a delay different from a delay of the second digital delay circuit.

13. A method comprising:
comparing magnitude and phase of a signal path of a first stage sub-analog-to-digital converter (sub-ADC) in a pipelined continuous-time analog-to-digital converter (CT ADC) with magnitude and phase of a continuous-time signal path of the pipelined CT ADC to generate a residue magnitude and phase, the continuous-time signal path comprising an input delay circuit, the residue magnitude and phase generated by a first summing circuit; and
varying a delay value of at least one digital delay circuit coupled to receive an output of the first stage sub-ADC and coupled to each of the first summing circuit and an output second summing circuit, the output summing circuit coupled to the at least one digital delay circuit, and an output of a final stage sub-ADC.

14. The method of claim 13 , wherein the input delay circuit is a passive filter network including at least one low-pass filter and at least one all-pass filter, the least one low-pass filter including at least one resistor-capacitor circuit and the at least one all-pass filter including at least one of: at least one resistor-capacitor circuit and at least one resistor-inductor-capacitor circuit.

15. The method of claim 13 , wherein the input delay circuit is at least one of: a digitally controlled delay and a transmission line producing a fixed delay.

16. The method of claim 13 , wherein the input delay circuit is positioned in the continuous-time signal path between an analog input signal of the pipelined CT ADC and the first summing circuit.

17. The method of claim 13 , wherein the delay value of the at least one digital delay circuit is varied for reducing residue magnitude and phase over at least one of: process, temperature, and voltage variations.

18. The method of claim 17 , wherein the at least one digital delay circuit is coupled to the first summing circuit via a sub-digital-to-analog converter, and coupled to the second summing circuit via a digital noise cancellation filter.

19. The method of claim 13 , the pipelined CT ADC is an integrated circuit and is a pipelined continuous-time delta sigma modulator (CT DSM), and the first stage sub-ADC is a first stage sub-delta sigma modulator (sub-DSM) of a plurality of pipelined.

Assignees

• Texas Instruments Inc

Inventors

• Srinivasan Venkatesh
• Shi Kun
• Wang Victoria
• Klemmer Nikolaus

Classifications

• H03M3/386

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03K5/159 Primary

  Applications of delay lines not covered by the preceding subgroups · CPC title

• H03M1/001

  Analogue/digital/analogue conversion · CPC title