Delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-10484004-B2
Application number	US-201816151404-A
Country	US
Kind code	B2
Filing date	Oct 4, 2018
Priority date	Mar 15, 2018
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.

First claim

What is claimed is:

1. A delta-sigma modulator (DSM) comprising:
a first loop filter for filtering a first signal to a second signal;
a second loop filter for filtering a third signal;
a comparator;
a register coupled to the comparator;
a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator;
a first path coupled between the register and the first loop filter, causing a delayed signal to be linearly combined with an input signal to form the first signal; and
a second path coupled between the register and the second loop filter, causing the delayed signal to be linearly combined with the second signal to form the third signal; wherein:
the delayed signal is formed by delaying an output signal of the register; and
during a second phase and a third phase, the first capacitor bank is conducted to the comparator; and
during a fourth phase and a repeated first phase, the second capacitor bank is conducted to the comparator.

2. The DSM of claim 1 further comprising:
a first sum circuit coupled to the input signal, the delayed signal and the first loop filter, for linearly combining the delayed signal and the input signal.

3. The DSM of claim 1 further comprising:
a delay circuit coupled to the register, for delaying the output signal to form the delayed signal.

4. The DSM of claim 3 , wherein:
the output signal is sampled at a sampling period; and
the delay circuit delays the output signal by one said sampling period to form the delayed signal.

5. The DSM of claim 1 further comprising:
a second sum circuit coupled to the delayed signal, the first loop filter and the second loop filter, for linearly combining the delayed signal and the second signal.

6. The DSM of claim 1 , wherein:
during a first phase, a fifth signal resulting from the second loop filter is conducted to the first capacitor bank;
during the third phase, the fifth signal is conducted to the second capacitor bank.

7. The DSM of claim 6 , wherein the second loop filter filters the third signal to a fourth signal, and the DSM further comprises:
a third sum circuit coupled to the first loop filter and the second loop filter, for linearly combining the second signal and the fourth signal to form the fifth signal.

8. The DSM of claim 6 further comprising:
a third path conducting the output signal to the first capacitor bank during the first phase; and
a fourth path conducting the output signal to the second capacitor bank during the third phase.

9. The DSM of claim 8 , wherein:
the third path stops conducting the output signal to the first capacitor bank during the third phase; and
the fourth path stops conducting the output signal to the second capacitor bank during the first phase.

10. The DSM of claim 1 , wherein the second loop filter is coupled between the first loop filter and a fifth node, and the DSM further comprises:
a first front switch coupled between the fifth node and the first capacitor bank; and
a second front switch coupled between the fifth node and the second capacitor bank; wherein
during a first phase, the first front switch is closed to conduct the fifth node to the first capacitor bank, and the second front switch is open to stop conducting the fifth node to the second capacitor bank; and
during the third phase, the second front switch is closed to conduct the fifth node to the second capacitor bank, and the first front switch is open to stop conducting the fifth node to the first capacitor bank.

11. The DSM of claim 10 , wherein:
during the second phase and the fourth phase, the first front switch and the second front switch are open.

12. The DSM of claim 1 further comprising:
a first back switch coupled between the first capacitor bank and the comparator; and
a second back switch coupled between the second capacitor bank and the comparator;
during the second phase and the third phase, the first back switch is closed to conduct the first capacitor bank to the comparator, and the second back switch is open to stop conducting the second capacitor bank to the comparator.

13. The DSM of claim 12 , wherein:
during a first phase and the fourth phase, the first back switch is open to stop conducting the first capacitor bank to the comparator, and the second back switch is closed to conduct the second capacitor bank to the comparator.

14. The DSM of claim 12 , wherein the first loop filter is implemented by a filter circuit which comprises:
a first interior switch coupled between the input signal and a first interior node;
a first interior capacitor coupled between the first interior node and a second interior node;
a second interior switch coupled between the second interior node and a third interior node;
an operational amplifier having an input terminal at the third interior node and an output terminal; and
a second interior capacitor coupled between the input terminal and the output terminal; wherein
during a first phase and the third phase, the first interior switch is closed to conduct the input signal to the first interior capacitor, and the second interior switch is open to stop conducting the first interior capacitor to the input terminal; and
during the second phase and the fourth phase, the second interior switch is closed to conduct the first interior capacitor to the input terminal, and the first interior switch is open to stop conducting the input signal to the first interior capacitor.

15. The DSM of claim 1 , wherein the first loop filter is a first-order integrator.

16. A DSM comprising:
a first sum circuit coupled to an input node, a ninth node and a first node;
a first loop filter coupled to the first node and a second node;
a second sum circuit coupled to the second node, the ninth node and a third node;
a second loop filter coupled to the third node and a fourth node;
a third sum circuit coupled to the second node, the fourth node and a fifth node;
a first capacitor bank and a second capacitor bank;
a first front switch coupled between the fifth node and the first capacitor bank;
a second front switch coupled between the fifth node and the second capacitor bank;
a first back switch coupled between the first capacitor bank and a sixth node;
a second back switch coupled between the second capacitor bank and the sixth node;
a comparator coupled to the sixth node and a seventh node;
a register coupled to the seventh node and an output node; and
a delay circuit coupled to the output node and the ninth node.

17. The DSM of claim 16 , wherein:
when the first front switch is closed, the second front switch is open; and
when the second front switch is closed, the first front switch is open.

18. The DSM of claim 16 , wherein:
when the first front switch is closed, the first back switch is open; and
when the first back switch is closed, the first front switch is open.

19. The DSM of claim 16 further comprising:
a first feedback switch coupled between the output node and the first capacitor bank; and
a second feedback switch coupled between the output node and the second capacitor bank.

20. A DSM comprising:
a first loop filter for filtering a first signal to a second signal;
a second loop filter for filtering a third signal;
a comparator;
a register coupled to the comparator;
a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator;
a delay circuit coupled to the register, for delaying an output

Assignees

• Mediatek Inc

Inventors

• Lo Tien-Yu

Classifications

• H03M3/47

  using time-division multiplexing · CPC title

• H03M3/426 Primary

  the quantiser being a successive approximation type analogue/digital converter · CPC title

• H03M3/438

  the modulator having a higher order loop filter in the feedforward path · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title