Sigma delta modulator, integrated circuit and method therefor

Patent metadata

Field	Value
Publication number	US-10439633-B2
Application number	US-201815926442-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	May 25, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

First claim

The invention claimed is:

1. A multi-bit continuous-time sigma-delta modulator (SDM), comprising:
an input configured to receive an input analog signal;
a first summing junction configured to subtract a feedback analog signal from the input analog signal and produce an analog output signal;
a loop filter configured to filter the analog output signal from the first summing junction;
an analog-to-digital converter (ADC) configured to convert the filtered analog output signal to a digital output signal, wherein the ADC comprises multiple per-bit parallel loops having a plurality of paths, each path comprising a respective latch coupled to an output of a current summing junction and configured to provide a one-bit contribution to the digital output signal, each loop configured to provide a per-bit current summation of the filtered analog output signal using static reference currents directly to an input of the respective latch such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal; and
a feedback path comprising a main digital-to-analog converter (DAC) configured to convert the digital output signal to the feedback analog signal and route the feedback analog signal to the first summing junction.

2. The multi-bit continuous-time SDM of claim 1 , wherein the current summing junction is configured to sum each of a current domain representation of the filtered analog output signal, a current domain bit representation of the multi-bit quantization digital output signal from an excess loop delay (ELD) DAC, and a respective static reference current for each path.

3. The multi-bit continuous-time SDM of claim 1 , wherein each path further comprises:
a voltage-to-current converter configured to receive the filtered analog output signal in a voltage domain and convert the filtered analog output signal into a current domain; and
an excess loop delay (ELD) DAC configured to convert one bit of the multi-bit quantization digital output signal to an analog form.

4. The multi-bit continuous-time SDM of claim 3 , wherein the ELD DAC is configured to convert one bit of the digital output signal to an analog form.

5. The multi-bit continuous-time SDM of claim 1 , wherein the plurality of paths comprise a plurality of quantizer paths, with each path comprising a transconductance amplifier as a voltage-to-current converter.

6. An integrated circuit comprising a multi-bit continuous-time sigma-delta modulator (SDM), comprising:
an input configured to receive an input analog signal;
a first summing junction configured to subtract a feedback analog signal from the input analog signal and produce an analog output signal;
a loop filter configured to filter the analog output signal from the first summing junction;
an analog-to-digital converter (ADC) configured to convert the filtered analog output signal to a digital output signal, wherein the ADC comprises multiple per-bit parallel loops having a plurality of paths, each path comprising a respective latch coupled to an output of a current summing junction and configured to provide a one-bit contribution to the digital output signal, each loop configured to provide a per-bit current summation of the filtered analog output signal applying static reference currents directly to an input of the respective latch such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal; and
a feedback path comprising a main digital-to-analog converter (DAC) configured to convert the digital output signal to the feedback analog signal and route the feedback analog signal to the first summing junction.

7. A method for generating a multi-bit quantization digital output signal by a multi-bit continuous-time sigma-delta modulator (SDM), the method comprising:
receiving an input analog signal;
subtracting a feedback analog signal from the input analog signal in a first summing junction to produce an analog output signal;
filtering the analog output signal from the first summing junction;
converting the filtered analog output signal to a digital output signal in an analog-to-digital converter (ADC) by providing a per-bit current summation of the filtered analog output signal that is a multi-bit quantization digital output signal using multiple per-bit parallel loops and static reference currents in the ADC, wherein the ADC comprises multiple per-bit parallel loops comprising a plurality of paths, each path comprising a respective latch coupled to an output of a current summing junction and configured to provide a one-bit contribution to the digital output signal by applying static reference currents directly to an input of the respective latch;
converting the digital output signal, via a main digital-to-analog converter (DAC), to the feedback analog signal and routing the feedback analog signal to the first summing junction.

8. The method of claim 7 , wherein converting the filtered analog output signal to the digital signal in each path further comprises:
converting the filtered analog output signal to a current domain;
converting one bit of the multi-bit quantization digital output signal to an analog form by an excess loop delay (ELD) DAC; and
summing each of a current domain representation of the filtered analog output signal, a current domain bit representation of the multi-bit quantization digital output signal from the ELD DAC, and a dedicated reference current for each path.

9. The multi-bit continuous-time SDM of claim 2 , wherein the ELD DAC is a differential DAC.

10. The multi-bit continuous-time SDM of claim 9 , wherein the differential DAC is configured to provide a dynamic differential current.

Assignees

• Nxp Bv

Inventors

• Breems Lucien Johannes
• Bolatkale Muhammed
• Zhang Chenming

Classifications

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/42

  having multiple quantisers arranged in parallel loops · CPC title

• H03M3/322 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title