Analog-to-digital converter with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay compensation

Patent metadata

Field	Value
Publication number	US-9871534-B2
Application number	US-201715499872-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Jun 3, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

First claim

What is claimed is:

1. A quantizer comprising:
a multi-bit analog-to-digital converter (ADC), having an internal digital-to-analog converter (DAC) associated with comparison of each sampled analog input of the multi-bit ADC, wherein the multi-bit ADC converts a currently-sampled analog input into a first digital output, and a first noise-shaped truncation output is derived from the first digital output; and
a first DAC feedback circuit, configured to transfer a first truncation residue associated with the first noise-shaped truncation output to the internal DAC, wherein the transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

2. The quantizer of claim 1 , wherein the multi-bit ADC is a successive approximation register (SAR) ADC.

3. The quantizer of claim 1 , wherein the multi-bit ADC is a flash ADC.

4. The quantizer of claim 1 , wherein the first digital output of the multi-bit ADC comprises a most significant bit (MSB) part and a least significant bit (LSB) part, and the MSB part directly serves as the first noise-shaped truncation output, and the LSB part directly serves as the first truncation residue.

5. The quantizer of claim 1 , wherein the quantizer is implemented in a continuous-time delta-sigma modulator (CTDSM), and the first noise-shaped truncation output is a modulator output of the currently-sampled analog input.

6. The quantizer of claim 5 , wherein a dynamic element matching (DEM) circuit and a feedback DAC are located at a feedback path of the CTDSM; the multi-bit ADC determines the MSB part and the LSB part sequentially; and the DEM circuit and the feedback DAC process the MSB part while the multi-bit ADC is determining the LSB part.

7. The quantizer of claim 1 , wherein the multi-bit ADC further converts an earlier-sampled analog input into a second digital output; a second noise-shaped truncation output is derived from the second digital output; the first DAC feedback circuit further transfers a second truncation residue associated with the second noise-shaped truncation output to the internal DAC; the transferred second truncation residue is reflected in the comparison of the currently-sampled analog input of the multi-bit ADC via the internal DAC; a third noise-shaped truncation output is derived from the first noise-shaped truncation output; and the quantizer further comprises:
a second DAC feedback circuit, configured to transfer a third truncation residue associated with the third noise-shaped truncation output to the internal DAC, wherein the transferred third truncation residue is reflected in the comparison of the later-sampled analog input of the multi-bit ADC via the internal DAC; and
a first adder, configured to subtract a second truncation residue associated with the second noise-shaped truncation output from the third truncation residue to generate a fourth noise-shaped truncation output, wherein the third noise-shaped truncation output and the fourth noise-shaped truncation output are noise-shaped segmentation outputs of the currently-sampled analog input.

8. The quantizer of claim 7 , wherein the first digital output of the multi-bit ADC comprises a most significant bit (MSB) part, a central significant bit (CSB) part and a least significant bit (LSB) part, the MSB part directly serves as the third noise-shaped truncation output, the CSB part directly serves as the third truncation residue, and the LSB part directly serves as the first truncation residue.

9. The quantizer of claim 7 , wherein the quantizer is implemented in a continuous-time delta-sigma modulator (CTDSM), and the quantizer further comprises:
a second adder, configured to:
add the third noise-shaped truncation output to the fourth noise-shaped truncation output to generate a modulator output of the currently-sampled analog input; or
subtract the transferred second truncation residue from the first digital output to generate the modulator output of the currently-sampled input.

10. The quantizer of claim 9 , wherein a dynamic element matching (DEM) circuit and a feedback DAC are located at a feedback path of the CTDSM; the multi-bit ADC determines the MSB part, the CSB part and the LSB part sequentially; and the DEM circuit and the feedback DAC process the MSB part while the multi-bit ADC is determining the CSB part or the LSB part.

11. The quantizer of claim 7 , further comprising:
an excess loop delay (ELD) compensation circuit, configured to transfer an ELD compensation input to the internal DAC, wherein the ELD compensation input depends on the first digital output, and the transferred ELD compensation input is reflected in the comparison of the later-sampled analog input of the multi-bit ADC via the internal DAC.

12. The quantizer of claim 1 , further comprising:
an excess loop delay (ELD) compensation circuit, configured to transfer an ELD compensation input to the internal DAC, wherein the ELD compensation input depends on the first digital output, and the transferred ELD compensation input is reflected in the comparison of the later-sampled analog input of the multi-bit ADC via the internal DAC.

13. A quantizer comprising:
a multi-bit analog-to-digital converter (ADC), having an internal digital-to-analog converter (DAC) associated with comparison of each sampled analog input of the multi-bit ADC, wherein the multi-bit ADC converts a currently-sampled analog input into a first digital output and further converts an earlier-sampled analog input into a second digital output, a first noise-shaped truncation output is derived from the first digital output, and a second noise-shaped truncation output is derived from the second digital output; and
a DAC feedback circuit, configured to transfer a first truncation residue associated with the first noise-shaped truncation output to the internal DAC and further transfer a second truncation residue associated with the second noise-shaped truncation output to the internal DAC, wherein the transferred second truncation residue is reflected in comparison of the currently-sampled analog input of the multi-bit ADC via the internal DAC, and the transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC; and
a first adder, configured to subtract the second truncation residue from the first truncation residue to generate a third noise-shaped truncation output, wherein the first noise-shaped truncation output and the third noise-shaped truncation output are noise-shaped segmentation outputs of the currently-sampled analog input.

14. The quantizer of claim 13 , wherein the multi-bit ADC is a successive approximation register (SAR) ADC.

15. The quantizer of claim 13 , wherein the multi-bit ADC is a flash ADC.

16. The quantizer of claim 11 , wherein the first digital output of the multi-bit ADC comprises a most significant bit (MSB) part and a least significant bit (LSB) part, the MSB part directly serves as the first noise-shaped truncation output, and the LSB part directly serves as the first truncation residue.

17. The quantizer of claim 13 , wherein the quantizer is implemented in a continuous-time delta-sigma modulator (CTDSM), and the quantizer further comprises:
a second adder, configured to:
add the first noise-shaped truncation output to the third noise-shaped truncation output to generate a modulator output of the currently-sampled analog input; or
subtract the transferred second truncation residue from the first digital output to generate the modulator output of the

Assignees

• Mediatek Inc

Inventors

• Tsai Jen-Huan
• Lou Chih-Hong

Classifications

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H03M3/426 Primary

  the quantiser being a successive approximation type analogue/digital converter · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title