Sigma delta modulator and signal conversion method thereof

Patent metadata

Field	Value
Publication number	US-10069509-B2
Application number	US-201715693450-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Dec 1, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.

First claim

What is claimed is:

1. A sigma delta modulator, comprising:
a sigma delta modulating loop configured to process an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal, wherein the first clock signal has a clock cycle, the sigma delta modulating loop is configured to have a first delay time to compensate an excess loop delay associated with the sigma delta modulating loop, the first delay time is the same as M times of the clock cycle, and M is an integral multiple of 0.5 and is larger than 1; and
a plurality of adjusting loops configured to delay the quantized output signal for a plurality of second delay times, respectively, so as to generate the adjustment signal.

2. The sigma delta modulator of claim 1 , wherein the sigma delta modulating loop comprises:
a loop filter configured to filter a difference signal, so as to generate an analog signal, wherein the difference signal is a difference between the input signal and a feedback signal;
a calculation circuit configured to subtract the adjustment signal from the analog signal, so as to generate a calculation signal;
a sampling circuit configured to sample the calculation signal according to the first clock signal, so as to generate a sampled signal;
a quantizer configured to convert the sampled signal into the quantized output signal;
a first delay circuit configured to delay the quantized output signal for the first delay time, so as to generate a delay output signal; and
a digital-to-analog converter configured to convert the delay output signal into the feedback signal.

3. The sigma delta modulator of claim 2 , wherein the adjusting loops are coupled, in parallel, between the calculation circuit and the quantizer.

4. The sigma delta modulator of claim 2 , wherein a plurality of signal transmitting paths of the adjusting loops are without the loop filter.

5. The sigma delta modulator of claim 2 , wherein each one of the adjusting loops comprises:
a second delay circuit configured to delay the quantized output signal for a corresponding second delay time, so as to generate a delay adjustment signal; and
a second digital-to-analog converter configured to convert the delay adjustment signal, so as to generate the adjustment signal.

6. The sigma delta modulator of claim 5 , wherein the first delay circuit and the second delay circuit are implemented with a plurality of digital circuits, and the digital circuits are arranged, with a pipelined circuit configuration, in the sigma delta modulating loop and the adjusting loops.

7. The sigma delta modulator of claim 1 , wherein the sigma delta modulating loop is configured to process the input signal and the adjustment signal based on a transition edge of the first clock signal, so as to generate the quantized output signal.

8. The sigma delta modulator of claim 7 , wherein the adjusting loops comprise:
a first adjusting loop comprising a first flip-flop, wherein the first flip-flop is configured to generate a first delay adjustment signal based on a transition edge of a second clock signal and the quantized output signal, and the first clock signal and the second clock signal are different in phase by 180 degrees; and
a second adjusting loop comprising a second flip-flop, wherein the second flip-flop is configured to generate a second delay adjustment signal based on the transition edge of the second clock signal and the first delay adjustment signal,
wherein the first adjusting loop and the second adjusting loop are configured to generate the adjustment signal based on the first delay adjustment signal and the second delay adjustment signal.

9. The sigma delta modulator of claim 8 , wherein the sigma delta modulating loop comprises:
a third flip-flop configured to generate a delay output signal based on the transition edge of the first clock signal and the second delay adjustment signal,
wherein the sigma delta modulating loop is further configured to generate a feedback signal according to the delay output signal, so as to process the input signal.

10. The sigma delta modulator of claim 1 , wherein the second delay times are the same as 0.5−|Y−0.5| times of the clock cycle respectively, and Y is a positive integer that is larger than or equal to M.

11. The sigma delta modulator of claim 1 , wherein the second delay times are different from each other by N times of the clock cycle, and N is a positive integer that is larger than or equal to 1.

12. A signal conversion method, comprising:
processing an input signal and an adjustment signal based on a first clock signal by a sigma delta modulating loop, so as to generate a quantized output signal, wherein the first clock signal has a clock cycle, the sigma delta modulating loop is configured to have a first delay time to compensate an excess loop delay associated with the sigma delta modulating loop, the first delay time is the same as M times of the clock cycle, and M is an integral multiple of 0.5 and is larger than 1; and
delaying the quantized output signal for a plurality of second delay times, respectively, so as to generate the adjustment signal.

13. The signal conversion method of claim 12 , wherein the second delay times are the same as 0.5−|Y−0.5| times of the clock cycle respectively, and Y is a positive integer that is larger than or equal to M.

14. The signal conversion method of claim 12 , wherein generating the quantized output signal comprises:
filtering a difference signal to generate an analog signal, wherein the difference signal is a difference between the input signal and a feedback signal;
subtracting the adjustment signal from the analog signal, so as to generate a calculation signal;
sampling the calculation signal according to the first clock signal, so as to generate a sampled signal;
converting the sampled signal into the quantized output signal;
delaying the quantized output signal for the first delay time, so as to generate a delay output signal; and
generating the feedback signal based on the delay output signal.

15. The signal conversion method of claim 14 , wherein the second delay times are generated by a plurality of adjusting loops, the adjusting loops are coupled, in parallel, between a calculation circuit of the sigma delta modulating loop and a quantizer of the sigma delta modulating loop, the calculation circuit is configured to generate the calculation signal, and the quantizer is configured to generate the quantized output signal.

16. The signal conversion method of claim 12 , further comprising:
generating the first delay time and the second delay times by a plurality of digital circuits, wherein the digital circuits are arranged with a pipelined circuit configuration.

17. The signal conversion method of claim 12 , wherein generating the adjustment signal comprises:
delaying the quantized output signal for the second delay times, so as to generate a plurality of delay adjustment signals; and
converting the delay adjustment signals, so as to generate the adjustment signal.

18. The signal conversion method of claim 12 , wherein generating the quantized output signal comprises:
processing the input signal and the adjustment signal based on a transition edge of the first clock signal, so as to generate the quantized output signal, and
wherein generating the adjustment signal comprises:
generating a first delay adjustment signal based on a transition edge of a second clock signal and the quantized output signal, wherein the first clock signal and the second clock signal are differen

Assignees

• Realtek Semiconductor Corp

Inventors

• Zhou xiao-bo

Classifications

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/494

  Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/412 Primary

  characterised by the number of quantisers and their type and resolution · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title