Continuous-time delta-sigma ADC with scalable sampling rates and excess loop delay compensation

Patent metadata

Field	Value
Publication number	US-10243578-B2
Application number	US-201715440612-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Feb 23, 2017
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) comprising:
a loop filter;
a quantizer having an input coupled to an output of the loop filter;
one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and
a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer, wherein the clock delay circuit comprises: a replica latch replicating the data latch of one of the DACs and having an input coupled to the clock input for the ADC; and a clock generator having an input coupled to an output of the replica latch and an output coupled to the clock input for the quantizer.

2. The ADC of claim 1 , wherein the replica latch is configured to track process, voltage, and temperature (PVT) of the data latch of the one of the DACs.

3. The ADC of claim 1 , wherein the ADC has an excess loop delay (ELD) and wherein the ELD divided by a sampling period for the ADC remains constant regardless of changes in the sampling period.

4. The ADC of claim 3 , wherein the clock generator is configured to output a clock signal having a delay added to the output of the replica latch and wherein the delay is configured to be selected based on a sampling rate for the ADC, such that the ELD divided by the sampling period for the ADC remains constant.

5. The ADC of claim 4 , wherein the delay is a fixed percentage of the sampling period.

6. The ADC of claim 1 , wherein the clock generator comprises a delay-locked loop (DLL).

7. An analog-to-digital converter (ADC) comprising:
a loop filter;
a quantizer having an input coupled to an output of the loop filter; wherein the quantizer comprises: a combiner having a first input coupled to the input of the quantizer; and one or more excess loop delay (ELD) compensation paths, each ELD compensation path having an input coupled to the output of the quantizer and an output coupled to a second input of the combiner;
one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and
a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

8. The ADC of claim 7 , wherein each ELD compensation path has a compensation coefficient that remains fixed irrespective of a sampling rate for the ADC.

9. The ADC of claim 1 , wherein the quantizer comprises a time-to-digital converter configured to convert an analog input signal received from the loop filter at the input of the quantizer to a digital signal at the output of the quantizer.

10. An analog-to-digital converter (ADC) comprising:
a loop filter, wherein the loop filter comprises one or more integrator stages, each integrator stage comprising an operational amplifier with a tunable feedback capacitor configured to be adjusted based on a sampling rate for the ADC;
a quantizer having an input coupled to an output of the loop filter;
one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and
a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

11. The ADC of claim 10 , wherein the operational amplifier further comprises a transconductance adjusting circuit configured to adjust a transconductance of the operational amplifier based on the sampling rate for the ADC.

12. The ADC of claim 10 , wherein the operational amplifier further comprises a compensation circuit configured to adjust a location of a pole in the frequency response for the operational amplifier based on the sampling rate for the ADC.

13. The ADC of claim 1 , further comprising a decoder having an input coupled to an output of the quantizer and having an output coupled to each input of the DACs.

14. The ADC of claim 1 , wherein the ADC comprises a continuous-time delta-sigma modulator (CTDSM) ADC.

15. A method for sampling rate scaling in an analog-to-digital converter having a loop filter, a quantizer coupled to the loop filter, and one or more digital-to-analog converters (DACs) coupled between an output of the quantizer and one or more inputs of the loop filter, the method comprising:
changing a sampling frequency of the ADC;
clocking the one or more DACs with a first clock signal at the sampling frequency;
at least one of:
adjusting a first delay between the first clock signal and a second clock signal to scale with the sampling frequency; or
adjusting a bandwidth of an amplifier in the loop filter to scale with the sampling frequency; and

clocking the quantizer with the second clock signal at the sampling frequency.

16. The method of claim 15 , further comprising adjusting at least one capacitance of one or more integrators in the loop filter to scale with the sampling frequency.

17. The method of claim 15 , wherein adjusting the bandwidth of the amplifier in the loop filter comprises adjusting a biasing current in the amplifier such that a transconductance of the amplifier scales with the sampling frequency.

18. The method of claim 15 , wherein adjusting the first delay between the first clock signal and the second clock signal comprises setting the first delay as a percentage of a sampling period, the sampling period being an inverse of the sampling frequency.

19. The method of claim 15 , further comprising generating the second clock signal by adding the first delay and a second delay to the first clock signal, wherein the second delay matches a third delay in one of the DACs over process, voltage, and temperature (PVT).

20. The method of claim 15 , further comprising scaling excess loop delay (ELD) compensation coefficients with the sampling frequency, wherein the ELD compensation coefficients are applied to ELD compensation paths coupled to the quantizer.

Assignees

• Qualcomm Inc

Inventors

• Dagher Elias
• Wang Yan
• Zargham Mohammad Meysam
• Alladi Dinesh Jagannath

Classifications

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/396

  among different frequency bands · CPC title