ΔΣ modulator with excess loop delay compensation

Patent metadata

Field	Value
Publication number	US-10075181-B2
Application number	US-201715703840-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Jun 10, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

According to at least one aspect, a delta sigma modulator circuit is provided. The delta sigma modulator circuit includes a first signal processor circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal, a quantizer configured to generate a digital code using the processed signal, a second signal processor circuit configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit, and an digital-to-analog converter (DAC) configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

First claim

What is claimed is:

1. A delta sigma modulator circuit, comprising:
a first circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal;
a quantizer coupled to the first circuit and configured to generate a digital code comprising a plurality of bits using the processed signal;
a second circuit coupled to the quantizer and configured to receive the digital code, segment the digital code to form a segmented digital code that is smaller in size than the digital code and representative of all of the bits in the digital code, and generate a rotated digital code using the segmented digital code at least in part by rotating the segmented digital code to compensate for an excess loop delay in the circuit; and
a digital-to-analog converter (DAC) coupled between the second circuit and the first circuit and configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

2. The circuit of claim 1 , wherein the first circuit is configured to generate the processed signal at least in part by combining the feedback signal with the input signal to generate a combined signal and filtering the combined signal to generate the processed signal.

3. The circuit of claim 1 , wherein the digital code is coded using at least one coding scheme selected from the group consisting of: a phase-coding scheme and a thermometer-coding scheme.

4. The circuit of claim 1 , wherein the plurality of bits in the digital code is divided into a plurality of non-overlapping subsets of bits and wherein the second circuit is configured to generate the segmented digital code at least in part by identifying at least one most-significant bit (MSB) from each of the plurality of non-overlapping subsets of bits and identifying at least one least significant bit (LSB) from one of the plurality of non-overlapping subsets of bits.

5. The circuit of claim 4 , wherein the segmented digital code comprises a first portion and a second portion and wherein the second circuit is configured to generate the first portion of the segmented digital code using the identified at least one MSB from each of the plurality of non-overlapping subsets and generate the second portion of the segmented digital code using the identified at least one LSB from one of the plurality of non-overlapping subsets.

6. The circuit of claim 5 , wherein the rotated digital code comprises a first portion and a second portion and wherein the second circuit is configured to generate the first portion of the rotated digital code at least in part by rotating the first portion of the segmented digital code and configured to generate the second portion of the rotated digital code at least in part by rotating the second portion of the segmented digital code.

7. The circuit of claim 6 , wherein the DAC is a segmented DAC comprising a first DAC configured to receive the first portion of the rotated digital code and a second DAC configured to receive the second portion of the rotated digital code that is different from the first DAC.

8. The circuit of claim 1 , wherein the second circuit is configured to rotate the segmented digital code using at least a portion of a previously generated rotated digital code.

9. A delta sigma modulator circuit, comprising:
a first circuit configured to receive an input signal and a feedback signal and generate a processed signal using the input signal and the feedback signal;
a quantizer coupled to the first circuit and configured to generate a digital code comprising a plurality of bits using the processed signal;
a second circuit coupled to the quantizer and comprising:
a rotating splitter configured to receive the digital code and segment the digital code to form a segmented digital code that is smaller in size than the digital code and representative of all of the bits in the digital code; and
a rotation circuit configured to receive the segmented digital code and rotate the segmented digital code to generate a rotated digital code; and

a digital-to-analog converter (DAC) coupled between the second circuit and the first circuit and configured to receive the rotated digital code and generate the feedback signal using the rotated digital code.

10. The circuit of claim 9 , wherein the first circuit comprises:
a combiner configured to combine the feedback signal with the input signal to generate a combined signal; and
a loop filter configured to filter the combined signal to generate the processed signal.

11. The circuit of claim 9 , wherein the plurality of bits in the digital code is divided into a plurality of non-overlapping subsets of bits and wherein the rotating splitter is configured to generate the segmented digital code at least in part by:
generating a first portion of the segmented digital code comprising at least one most-significant bit (MSB) from each of the plurality of non-overlapping subsets of bits; and
generating a second portion of the segmented digital code comprising at least one least significant bit (LSB) from one of the plurality of non-overlapping subsets of bits.

12. The circuit of claim 11 , wherein the rotating splitter comprises:
a first gate array associated with a first subset of bits from the plurality of non-overlapping subsets of bits that comprises a first XOR gate having a first input configured to receive a state of an MSB from the first subset of bits and a second input configured to receive a state of an LSB from the first subset of bits; and
a second gate array associated with a second subset of bits from the plurality of non-overlapping subsets of bits that comprises a second XOR gate having a first input configured to receive a state of an MSB of the second subset of bits and a second input configured to receive a state of an LSB from the second subset of bits.

13. The circuit of claim 12 , wherein the rotating splitter comprises an OR gate having a first input configured to receive an output of the first XOR gate and a second input configured to receive an output of the second XOR gate.

14. The circuit of claim 11 , wherein the rotation circuit comprises:
a first rotator set comprising one or more rotators and being configured to generate a first portion of the rotated digital code at least in part by rotating the first portion of the segmented digital code; and
a second rotator set comprising one or more rotators and being configured to generate a second portion of the rotated digital code at least in part by rotating the second portion of the segmented digital code.

15. The circuit of claim 14 , wherein the DAC is a segmented DAC comprising a first DAC configured to receive the first portion of the rotated digital code and a second DAC configured to receive the second portion of the rotated digital code that is different from the first DAC.

16. The circuit of claim 11 , wherein the first portion of the segmented digital code is coded in a first coding scheme and the second portion of the segmented digital code is coded in a second coding scheme that is different from the first coding scheme.

17. The circuit of claim 16 , wherein the second circuit further comprises a conversion circuit configured to convert an input code from being coded in the first coding scheme to being coded in the second coding scheme.

18. A method of operating a delta sigma modulator circuit, comprising:
receiving, by a first circuit, an input signal;
generating, by the first circuit, a processed signal using the input signal and a feedback signal;
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Assignees

• Huang Sheng Jui
• Egan Nathan
• Kesharwani Divya
• Ashburn Jr Michael A
• Op T Eynde Frank
• Mediatek Inc

Inventors

• Huang Sheng-Jui
• Egan Nathan
• Kesharwani Divya
• Ashburn Jr Michael A
• Op 'T Eynde Frank

Classifications

• H03M3/422 Primary

  having one quantiser only · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/86

  with intermediate conversion to frequency of pulses · CPC title

• H03M3/37

  Compensation or reduction of delay or phase error · CPC title

• H03M3/428

  with lower resolution, e.g. single bit, feedback · CPC title