Selective etching process for SiGe and doped epitaxial silicon
US-12062571-B2 · Aug 13, 2024 · US
Electricity
Electricity · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H01L21/76256 |
| Official title | — |
| Display label | Electricity (mapped technology topic) |
| Total patents | 204 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 15 |
| 2016 | 17 |
| 2017 | 24 |
| 2018 | 17 |
| 2019 | 33 |
| 2020 | 21 |
| 2021 | 18 |
| 2022 | 13 |
| 2023 | 21 |
| 2024 | 10 |
| 2025 | 14 |
| 2026 | 1 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Methods of forming integrated circuitry
US-10103053-B1 · Oct 16, 2018 · US
Semiconductor devices on two sides of an isolation layer
US-2018061766-A1 · Mar 1, 2018 · US
Device layer transfer with a preserved handle wafer section
US-2018005873-A1 · Jan 4, 2018 · US
Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer
US-9837302-B1 · Dec 5, 2017 · US
Methods of fabricating silicon-on-insulator (soi) semiconductor devices using blanket fusion bonding
US-2017330792-A1 · Nov 16, 2017 · US
Device layer transfer with a preserved handle wafer section
US-9818637-B2 · Nov 14, 2017 · US
Wafer stack and fabrication method thereof
US-2017316969-A1 · Nov 2, 2017 · US
Bulk to silicon on insulator device
US-2017294340-A1 · Oct 12, 2017 · US
Bulk to silicon on insulator device
US-9786546-B1 · Oct 10, 2017 · US
Method of manufacturing a germanium-on-insulator substrate
US-2017271201-A1 · Sep 21, 2017 · US
Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby
US-2017271207-A9 · Sep 21, 2017 · US
Redistribution layer contacting first wafer through second wafer
US-9754860-B2 · Sep 5, 2017 · US
Low temperature adhesive resins for wafer bonding
US-9748131-B2 · Aug 29, 2017 · US
Semiconductor-on-insulator with back side strain inducing material
US-9748272-B2 · Aug 29, 2017 · US
Method for producing hybrid substrate, and hybrid substrate
US-9741603-B2 · Aug 22, 2017 · US
Methods of fabricating silicon-on-insulator (SOI) semiconductor devices using blanket fusion bonding
US-9721832-B2 · Aug 1, 2017 · US
Methods of forming III-V semiconductor structures using multiple substrates, and semiconductor devices fabricated using such methods
US-9716164-B2 · Jul 25, 2017 · US
Semiconductor device and manufacturing method thereof
US-2017200686-A1 · Jul 13, 2017 · US
Bulk layer transfer wafer with multiple etch stop layers
US-9704738-B2 · Jul 11, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H01L21/76256?
- CPC H01L21/76256 is the Cooperative Patent Classification code for “Electricity.”
- How many patents are filed under CPC H01L21/76256 (Electricity)?
- Our database includes 204 publications tagged with this CPC code.
- Is patent activity under CPC H01L21/76256 growing?
- Publication counts under this code: 10 in 2024 vs 14 in 2025 (latest complete years).