Methods of forming III-V semiconductor structures using multiple substrates, and semiconductor devices fabricated using such methods

Patent metadata

Field	Value
Publication number	US-9716164-B2
Application number	US-201314430513-A
Country	US
Kind code	B2
Filing date	Sep 3, 2013
Priority date	Sep 24, 2012
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
epitaxially growing a III-V base layer over a surface of a first substrate in a first deposition chamber, the first substrate comprising metallic molybdenum or a metallic molybdenum alloy, the first substrate exhibiting a first average CTE, the III-V base layer comprising a III-V semiconductor material exhibiting a second average CTE within about 10% or less of the first average CTE;
transferring the III-V base layer from the surface of the first substrate to a surface of a second substrate;
after transferring the III-V base layer to the second substrate, epitaxially growing a first III-V device layer and on an exposed surface of the III-V base layer in a second deposition chamber separate from the first deposition chamber, and epitaxially growing a second III-V device layer on the first III-V device layer in the second deposition chamber while the III-V base layer is disposed on the second substrate, the first III-V device layer having first material composition, the second III-V device layer having a second material composition differing from the first material composition so as to define an electron channel of at least one transistor proximate a heterojunction between the first III-V device layer and the second III-V device layer;
providing a first source contact and a second source contact of the at least one transistor in electrical contact with the second III-V device layer and in electrical communication with the electron channel;
providing a gate structure of the at least one transistor proximate the electron channel between the first source contact and the second source contact;
temporarily bonding a carrier substrate over the first source contact, the second source contact, and the gate structure;
removing second substrate from the III-V base layer and exposing a surface of the III-V base layer;
providing a layer of conductive material over at least a portion of the exposed surface of the III-V base layer, the layer of conductive material defining a drain contact of the at least one transistor; and
providing a dielectric material over the drain contact on a side thereof opposite the III-V base layer;
wherein the at least one transistor comprises a vertical high electron mobility transistor.

2. The method of claim 1 , further comprising configuring the at least one transistor to comprise a pseudomorphic high electron mobility transistor.

3. The method of claim 1 , wherein epitaxially growing the III-V base layer over the surface of the first substrate comprises epitaxially growing a polar III-V semiconductor material over the surface of the first substrate, and wherein growing the first III-V device layer on the exposed surface of the III-V base layer comprises growing the first III-V device layer on a Group V face of the polar III-V semiconductor material.

4. The method of claim 1 , further comprising:
selecting the III-V base layer to comprise a first binary III-V semiconductor material and selecting the first binary III-V semiconductor material to comprise GaN;
selecting the first III-V device layer to comprise a ternary III-V semiconductor material and selecting the ternary III-V semiconductor material to comprise AlGaN; and
selecting the second III-V device layer to comprise a second binary III-V semiconductor material and selecting the second binary III-V semiconductor material to comprise GaN.

5. The method of claim 1 , further comprising:
selecting the first material composition of the first III-V device layer to exhibit a first energy bandgap; and
selecting the second material composition of the second III-V device layer to exhibit a second energy bandgap differing from the first energy bandgap, a conduction band in an energy band structure within the first III-V device layer and the second III-V device layer extending below a Fermi energy level proximate the heterojunction such that a two-dimensional electron gas is defined in at least one of the first III-V device layer and the second III-V device layer proximate the heterojunction.

6. The method of claim 1 , further comprising selecting the second substrate to comprise a second substrate material exhibiting a third average CTE differing from the first average CTE.

7. The method of claim 6 , further comprising selecting the second substrate material to comprise silicon.

Assignees

• Soitec Silicon On Insulator

Inventors

• Sadaka Mariam

Classifications

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/07331

  Connecting techniques · CPC title