Wafer stack and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2017316969-A1
Application number	US-201615219523-A
Country	US
Kind code	A1
Filing date	Jul 26, 2016
Priority date	May 2, 2016
Publication date	Nov 2, 2017
Grant date	—

Abstract

A semiconductor device includes a first wafer and a second wafer. The first wafer has a top portion. The second wafer is disposed on the top portion of the first wafer, wherein the second wafer has a bottom portion bonded on the top portion of the first wafer, and a non-bonded area of the bottom portion has a width smaller than 0.5 mm. The bottom portion of the second wafer has a size smaller than or equal to that of the top portion of the first wafer. In some embodiments, the top portion of the first wafer has first rounded corners, and the bottom portion of the second wafer has second corners. A cross-sectional view of each of the second rounded corners has a radius smaller than that of each of first rounded corners. In some embodiments, the bottom portion of the second wafer has right angle corners.

First claim

1 . semiconductor device, comprising:
a first wafer having a top portion, wherein the top portion has a top surface, and a cross-sectional view of the first wafer has a first wafer width defined by a plurality of first side surfaces adjacent to the top surface; and a second wafer disposed on the top portion of the first wafer to enable a bottom surface of a bottom portion of the second wafer to be bonded on the top surface of the first wafer, wherein a cross-sectional view of the second wafer has a second wafer width defined by a plurality of second side surfaces adjacent to the bottom surface, and the second wafer width is smaller than the first wafer width of the first wafer, and a non-bonded area of the bottom surface of the bottom portion of the second wafer has a width smaller than 0.5 mm.

2 . The semiconductor device of claim 1 , wherein the bottom portion of the second wafer is bonded on the top portion of the first wafer by a fusion bonding process, an anodic bonding process, or an adhesive bonding process.

3 . The semiconductor device of claim 1 , wherein the bottom portion of the second wafer is located within an area defined by the top portion of the first wafer.

4 . The semiconductor device of claim 1 , wherein a cross-sectional view of the bottom portion of the second wafer has a plurality of right angle corners.

5 . The semiconductor device of claim 1 , wherein a cross-sectional view of the top portion of the first wafer has a plurality of first rounded corners, and a cross-sectional view of the bottom portion of the second wafer has a plurality of second rounded corners each having a radius smaller than that of each of the first rounded corners.

6 . The semiconductor device of claim 1 , further comprising a third wafer disposed on the second wafer, wherein the third wafer has a bottom portion bonded on a top portion of the second wafer, and a cross-sectional view of the third wafer has a third wafer width smaller than or equal to the second wafer width of the second wafer.

7 . The semiconductor device of claim 6 , wherein a cross-sectional view of the bottom portion of the third wafer has a plurality of right angle corners.

8 . The semiconductor device of claim 6 , wherein a cross-sectional view of the top portion of the second wafer has a plurality of second rounded corners, and a cross-sectional view of the bottom portion of the third wafer has a plurality of third rounded corners each having a radius smaller than that of each of the second rounded corners.

9 . The semiconductor device of claim 1 , wherein the second wafer width is smaller than that of the first wafer width by 0.1 mm to 10 mm.

10 . A semiconductor device, comprising:
a first wafer having a top portion, wherein the top portion has a top surface, and a cross-sectional view of the top portion of the first wafer has a first wafer width defined by a plurality of first side surfaces adjacent to the top surface; and a second wafer disposed on the top portion of the first wafer to enable a bottom surface of a bottom portion of the second wafer to be bonded on the top surface of the first wafer, wherein a cross-sectional view of the bottom portion of the second wafer has a second wafer width defined by a plurality of second side surfaces adjacent to the bottom surface, and the second wafer width is the same as the first wafer width, and a non-bonded area of the bottom surface of the bottom portion of the second wafer has a width smaller than 0.5 mm.

11 . The semiconductor device of claim 10 , wherein the cross-sectional view of the top portion of the first wafer has a plurality of first rounded corners, and the cross-sectional view of the bottom portion of the second wafer has a plurality of second rounded corners each having a radius smaller than that of each of the first rounded corners.

12 . The semiconductor device of claim 11 , wherein the bottom portion of the second wafer is bonded on the top portion of the first wafer by a fusion bonding process, an anodic bonding process, or an adhesive bonding process.

13 . The semiconductor device of claim 11 , further comprising a third wafer disposed on the second wafer, wherein the third wafer has a bottom portion bonded on a top portion of the second wafer, and a cross-sectional view of the third wafer has a third wafer width smaller than or equal to the second wafer width of the second wafer.

14 . A fabrication method of a semiconductor device, comprising:
providing a first wafer having a top portion, wherein the top portion has a top surface, and a cross-sectional view of the top portion of the first wafer has a first wafer width defined by a plurality of first side surfaces adjacent to the top surface; providing a second wafer having a bottom portion, wherein the bottom portion has a bottom surface, and a cross-sectional view of the bottom portion of the second wafer has a second wafer width defined by a plurality of second side surfaces adjacent to the bottom surface, and the second wafer width is smaller than or equal to the first wafer width; and bonding the bottom portion of the second wafer on the top portion of the first wafer to enable the bottom surface of the second wafer to be bonded on the top surface of the first wafer; wherein a non-bonded area of the bottom surface of the bottom portion of the second wafer has a width smaller than 0.5 mm.

15 . The fabrication method of claim 14 , wherein when the second wafer width is equal to the first wafer width, a cross-sectional view of the top portion of the first wafer has a plurality of first rounded corners, and a cross-sectional view of the bottom portion of the second wafer has a plurality of second rounded corners each having a radius smaller than that of each of first rounded corners of the top portion of the first wafer.

16 . The fabrication method of claim 14 , further comprising: performing a thin-down process on the second wafer after the operation for bonding the bottom portion of the second wafer on the top portion of the first wafer to decrease a thickness of the second wafer.

17 . The fabrication method of claim 16 , wherein the thin-down process applies a force on a top portion of the second wafer, and the bonding process is a fusion bonding process, an anodic bonding process, or an adhesive bonding process.

18 . The fabrication method of claim 15 , wherein when the second wafer width is smaller than the first wafer width, a cross-sectional view of the top portion of the first wafer has a plurality of first rounded corners, and a cross-sectional view of the bottom portion of the second wafer has a plurality of second rounded corners each having a radius smaller than that of each of first rounded corners of the top portion of the first wafer.

19 . The fabrication method of claim 15 , wherein when the second wafer width is smaller than the first wafer width, a cross-sectional view of a cross-sectional view of the bottom portion of the second wafer has a plurality of right angle corners.

20 . The semiconductor device of claim 15 , wherein when the second wafer width is smaller than the first wafer width, the second wafer width is smaller than the first wafer width by 0.1 mm to 10 mm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Kuei-Sung
• Chen Ching-Ray
• Liu Yen-Cheng
• Tsai Shang-Ying

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W72/0198

  batch processes · CPC title

• H10P90/1922 Primary

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H01L21/304

  Electricity · mapped topic

• H01L2224/94

  Electricity · mapped topic