Methods of forming integrated circuitry

Patent metadata

Field	Value
Publication number	US-10103053-B1
Application number	US-201715650274-A
Country	US
Kind code	B1
Filing date	Jul 14, 2017
Priority date	Jul 14, 2017
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the dielectric region, an insulative wall laterally surrounding a volume of the first semiconductor material, and a first doped region along a lower surface of the first semiconductor material. The first semiconductor material is patterned to form a pillar within a tub. The pillar has top and bottom portions. An upper doped region is formed within the pillar top portion. A dielectric liner is formed to extend along the pillar, and to extend along the bottom of the tub. Conductive gate material is formed within the tub and over the dielectric liner. The lower and upper doped regions within the pillar are first and second source/drain regions, respectively, and the conductive gate material includes a transistor gate which gatedly couples the first and second source/drain regions.

First claim

I claim:

1. A method of forming integrated circuitry, comprising:
forming a structure having a first semiconductor material over a dielectric bonding region, having a second semiconductor material under the dielectric bonding region, having an insulative wall laterally surrounding a volume of the first semiconductor material, and having a first doped region along a lower surface of the first semiconductor material;
patterning said volume of the first semiconductor material to form a pillar within a tub; the pillar extending upwardly from a first area of the first doped region; a bottom of the tub being along a second area of the first doped region within said volume; the pillar having a bottom portion and a top portion; the first area of the first doped region being a lower doped region within the pillar;
forming an upper doped region within the top portion of the pillar;
forming a dielectric liner to extend along a sidewall of the pillar, and to extend over the second area of the first doped region along the bottom of the tub; and
forming conductive gate material within the tub and over the dielectric liner; the lower and upper doped regions comprising first and second source/drain regions, respectively, and the conductive gate material comprising a transistor gate; the first and second source/drain regions being gatedly coupled to one another by the transistor gate.

2. The method of claim 1 wherein the forming of the structure includes:
forming a first assembly comprising a first dielectric bonding material over the first semiconductor material, the first assembly comprising the insulative wall extending downwardly into the first semiconductor material;
forming a second assembly comprising a second dielectric bonding material over the second semiconductor material;
inverting the first assembly and bonding the first dielectric bonding material with the second dielectric bonding material to form the dielectric bonding region and thereby bond the first and second assemblies to one another; after bonding the first and second assemblies to one another, an upper surface of the first assembly comprising the first semiconductor material extending upwardly to above the insulative wall; and
polishing said upper surface of the first assembly to form a planarized surface extending across the first semiconductor material and the insulative wall.

3. The method of claim 2 comprising forming third semiconductor material over the upper surface of the first assembly prior to the polishing.

4. The method of claim 3 wherein the third semiconductor material comprises boron-doped silicon.

5. The method of claim 1 wherein a second doped region is formed along a top surface of the volume of the first semiconductor material prior to forming the pillar, and wherein the upper doped region within the top portion of the pillar is patterned from the second doped region.

6. The method of claim 1 wherein the upper doped region is implanted into the top portion of the pillar after forming the pillar.

7. The method of claim 1 wherein said pillar is one of two pillars formed within the tub.

8. The method of claim 7 wherein said two pillars are comprised by two neighboring DRAM cells which share a wordline connection.

9. The method of claim 7 wherein said two pillars are comprised by a driver transistor and a load transistor of an inverter of an SRAM cell.

10. A method of forming integrated circuitry, comprising:
forming a hybrid structure comprising an upper structure over a dielectric bonding region and comprising a lower structure under the dielectric bonding region; the upper structure having a first semiconductor material, having an insulative periphery laterally surrounding the first semiconductor material, and having a lower doped region along a lower surface of the first semiconductor material; the lower structure having a second semiconductor material;
patterning a first portion of the first semiconductor material into a pair of neighboring pillars, a remaining second portion of the first semiconductor material being recessed relative said first portion; each of the pillars having a bottom portion and a top portion, with the bottom portion including a segment of the lower doped region; the pillars being a first pillar and a second pillar;
forming upper doped regions within the top portions of the pillars;
forming a dielectric liner to extend along sidewalls of the pillars, and to extend along said remaining second portion of the first semiconductor material; and
forming conductive gate material along the dielectric liner and within a container bounded by the insulative periphery; the lower and upper doped regions within the first pillar comprising first and second source/drain regions, respectively, and the conductive gate material comprising a first transistor gate which gatedly couples the first and second source/drain regions to one another; the lower and upper doped regions within the second pillar comprising third and fourth source/drain regions, respectively, and the conductive gate material comprising a second transistor gate which gatedly couples the third and fourth source/drain regions to one another.

11. The method of claim 10 wherein the first transistor gate, first source/drain region and second source/drain are together comprised by a first DRAM cell; and wherein the second transistor gate, third source/drain region and fourth source/drain region are together comprised by a second DRAM cell.

12. The method of claim 11 wherein:
the upper structure includes a block of insulative material extending through the lower doped region;
the first pillar is formed to be on one side of said block of insulative material;
the second pillar is formed to be on another side of said block of insulative material; and
the block of insulative material isolates the first source/drain region from the third source/drain region.

13. The method of claim 10 wherein the first transistor gate, first source/drain region and second source/drain are together comprised by a driver transistor of an inverter of an SRAM cell; and wherein the second transistor gate, third source/drain region and fourth source/drain region are together comprised by a load transistor of the inverter of the SRAM cell.

14. The method of claim 13 wherein:
the first semiconductor material of the upper structure comprises p-type monocrystalline silicon;
the upper structure includes a block of insulative material extending through the lower doped region; the lower doped region being an n-type region on a first side of the block of insulative material, and being a p-type region on a second side of the block of insulative material; a segment of the n-type region being the first source/drain region and a segment of the p-type region being the third source/drain region;
the first pillar is formed to be on the first side of said block of insulative material, and the second pillar is formed to be on the second side of said block of insulative material;
a section of the second pillar over the third source/drain region is counter-doped to be n-type;
the second source/drain region is formed to be n-type and the fourth source/drain region is formed to be p-type;
the first source/drain region is coupled with a first reference voltage; and
the third source/drain region is coupled with a second reference voltage which is higher than the first reference voltage.

15. A method of forming integrated circuitry, comprising:
forming a first assembly which has an insulative boundary structure laterally surrounding a region of a first semiconductor material, which has a firs

Assignees

• Micron Technology Inc

Inventors

• Sukekawa Mitsunari

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10P90/1922 Primary

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H01L21/76898

  Electricity · mapped topic