Bulk to silicon on insulator device

Patent metadata

Field	Value
Publication number	US-2017294340-A1
Application number	US-201615091866-A
Country	US
Kind code	A1
Filing date	Apr 6, 2016
Priority date	Apr 6, 2016
Publication date	Oct 12, 2017
Grant date	—

Abstract

A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

First claim

1 . A method for forming a semiconductor device, the method comprising:
forming a fin in a bulk semiconductor substrate; depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin; removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin; depositing an etch stop layer on the first insulator layer; forming a gate stack over a channel region of the fin and over portions of a first surface of the etch stop layer; removing a portion of the bulk semiconductor substrate to expose portions of a second surface of the etch stop layer and the fin; and depositing a second insulator layer over exposed portions of the fin and the second surface of the etch stop layer.

2 . The method of claim 1 , further comprising:
depositing a bonding film on the etch stop layer and the gate stack after forming the gate stack; bonding a handle wafer to the bonding film; and removing the handle wafer from the bonding film following the depositing the second insulator layer.

3 . The method of claim 1 , further comprising:
removing portions of the second insulator layer and the etch stop layer to expose a source/drain region; and depositing a contact material on the source/drain region.

4 . The method of claim 1 , wherein the first insulator layer includes an oxide material.

5 . The method of claim 1 , wherein the etch stop layer includes a nitride material.

6 . The method of claim 2 , further comprising depositing a third insulator layer over portions of the fin prior to depositing the bonding film.

7 . The method of claim 1 , wherein the removing portions of the bulk semiconductor substrate to expose portions of the etch stop layer and the fin includes performing a planarizing process.

8 . The method of claim 2 , further comprising forming a source/drain region on the fin prior to depositing the bonding film on the etch stop layer and the gate stack.

9 . The method of claim 8 , further comprising prior to depositing the bonding film, forming conductive contacts on the source/drain region.

10 . A method for forming a semiconductor device, the method comprising:
depositing a first insulator layer on a bulk semiconductor substrate; depositing an etch stop layer on the first insulator layer; depositing a second insulator layer on the etch stop layer; removing a portion of the second insulator layer, the etch stop layer, and the first insulator layer to form a cavity that exposes a portion of the bulk semiconductor substrate; growing a semiconductor fin in the cavity; removing the second insulator layer to expose the etch stop layer and sidewalls of the fin; forming a gate stack over a channel region of the fin and over portions of a first surface of the etch stop layer; removing portions of the bulk semiconductor substrate to expose portions of a second surface of the etch stop layer and to expose portions of the fin, said second surface opposite the first surface of the etch stop layer; and depositing a third insulator layer over exposed portions of the fin and the second surface of the etch stop layer.

11 . The method of claim 10 , further comprising:
depositing a bonding film on the etch stop layer and the gate stack after forming the gate stack; bonding a handle wafer to the bonding film; and removing the handle wafer from the bonding film following the depositing the third insulator layer.

12 . The method of claim 10 , further comprising:
removing portions of the third insulator layer and the etch stop layer to expose a source/drain region; and depositing a contact material on the source/drain region.

13 . The method of claim 10 , wherein the first insulator layer includes an oxide material.

14 . The method of claim 10 , wherein the etch stop layer includes a nitride material.

15 . The method of claim 11 , further comprising depositing a third insulator layer over portions of the fin prior to depositing the bonding film.

16 . The method of claim 10 , wherein the removing portions of the bulk semiconductor substrate to expose portions of the etch stop layer and the fin includes performing a planarizing process.

17 . The method of claim 11 , further comprising forming a source/drain region on the fin prior to depositing the bonding film on the etch stop layer and the gate stack.

18 . The method of claim 11 , further comprising prior to depositing the bonding film, forming conductive contacts on the source/drain region.

19 . A semiconductor device comprising:
an insulator layer; a semiconductor fin arranged on the insulator layer; an etch stop layer arranged on the insulator layer adjacent to the semiconductor fin; and a gate stack arranged over a channel region of the semiconductor fin and the etch stop layer.

20 . The device of claim 19 , wherein the semiconductor fin includes a crystalline semiconductor material.

Assignees

• IBM

Inventors

• Hook Terence B
• Rubin Joshua M
• Yamashita Tenko

Classifications

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P14/272

  using mask materials other than SiO2 or SiN · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title