Methods of fabricating silicon-on-insulator (SOI) semiconductor devices using blanket fusion bonding

Patent metadata

Field	Value
Publication number	US-9721832-B2
Application number	US-201313834329-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.

First claim

What is claimed is:

1. A method for fabricating a silicon-on-insulator device, comprising:
bonding a first semiconductor wafer, having a base layer, a degenerately doped layer disposed on the base layer, and a first unannealed oxidized layer disposed on the doped layer, to a second semiconductor wafer having a second oxidized layer disposed thereon, wherein the degenerately doped layer is doped to a generally uniform depth through the unannealed oxidized layer, and further wherein the bond is between the first oxidized layer and the second oxidized layer;
removing the base layer of the first semiconductor wafer to expose the doped layer; and
patterning the exposed doped layer to define a piezoresistive pattern on the second doped side of the doped layer.

2. The method of claim 1 , wherein the doped layer is blanket doped.

3. A method for fabricating a silicon-on-insulator (SOI) device, comprising:
oxidizing a surface of a first semiconductor wafer to produce an oxidized layer having an oxidized surface, the first semiconductor wafer having a base layer;
degenerately doping the first semiconductor wafer through the oxidized layer to produce a doped layer having a first doped side and a second doped side;
bonding the oxidized surface of the first semiconductor wafer to an oxidized second semiconductor wafer;
removing the base layer from the first semiconductor wafer, without use of a buried oxide etch stop, to expose the second doped side of the doped layer; and
patterning the exposed second doped side of the doped layer to define a piezoresistive pattern on the second doped side of the doped layer.

4. The method of claim 3 , wherein the doped layer is blanket doped.

5. The method of claim 3 , wherein the doped layer is P++ boron doped.

6. The method of claim 3 , wherein the bonding occurs between about 800° C. and 1200° C.

7. The method of claim 3 , further comprising defining a diaphragm member in the oxidized second semiconductor wafer.

8. The method of claim 3 , wherein the oxidized second semiconductor wafer has a thickness that is determined based on a desired pressure range.

9. The method of claim 3 , wherein the oxidized layer has a thickness of about 200 angstroms or less.

10. The method of claim 3 , wherein the oxidized second semiconductor wafer has an oxide layer that is thicker than the oxidized layer of the first semiconductor wafer.

11. The method of claim 3 , wherein the exposed second doped side of the doped layer is patterned using RIE-reactive ion etching techniques.

12. The method of claim 3 , wherein the exposed second doped side of the doped layer is patterned using wet etching techniques.

13. The method of claim 3 , wherein the degenerate doping is done through diffusion.

14. The method of claim 3 , wherein the bonding of the oxidized surface of the first semiconductor wafer to the oxidized second semiconductor layer occurs without annealing the oxidized surface of the first semiconductor wafer.

15. A method for fabricating a silicon-on-insulator (SOI) device, comprising:
oxidizing a surface of a first semiconductor wafer to produce a first oxidized layer having a first oxidized surface, the first semiconductor wafer having a base layer;
degenerately doping the first semiconductor wafer through the first oxidized layer to produce a doped layer below the first oxidized layer, the doped layer having a first doped side and a second doped side;
doping the first oxidized surface to provide a doped skin;
oxidizing a surface of a second semiconductor wafer to produce a second oxidized layer having a second oxidized surface;
bonding the first oxidized surface to the second oxidized surface;
removing the base layer from the first semiconductor wafer to expose the second doped side of the doped layer; and
patterning the exposed second doped side of the doped layer to define a piezoresistive pattern on the second doped side of the doped layer.

16. The method of claim 15 , wherein the first oxidized layer further has a first thickness and wherein the second oxidized surface has a second thickness that is thicker than the first thickness.

17. The method of claim 15 , wherein the exposed second doped side of the doped layer is patterned using RIE-reactive ion etching techniques.

Assignees

• Kulite Semiconductor Products Inc

Inventors

• Ned Alexander A
• Stefanescu Sorin
• Vandeweert Joseph R

Classifications

• H10P72/7432

  used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title