Bulk layer transfer wafer with multiple etch stop layers

Patent metadata

Field	Value
Publication number	US-9704738-B2
Application number	US-201514740505-A
Country	US
Kind code	B2
Filing date	Jun 16, 2015
Priority date	Jun 16, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, multiple etch stop layers are formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layers are incorporated into in a layer transfer process to enable very thin high quality active device layers of substantially uniform across-wafer thickness to be separated from bulk semiconductor wafers and bonded to handle wafers. As a result, these examples can produce high-performance and low-power semiconductor devices while avoiding the high cost of SOI wafers.

First claim

What is claimed is:

1. A method, comprising:
creating an etch stop trench in a top portion of a semiconductor wafer;
forming a first etch stop material in the etch stop trench;
producing a second etch stop material on the first etch stop material;
fabricating a device layer in the top portion of the semiconductor wafer, wherein the device layer comprises an active device;
bonding the semiconductor wafer to a handle wafer with the top portion of the semiconductor wafer facing the handle wafer;
after the bonding, thinning a bottom side of the semiconductor wafer to a bottom portion of the first etch stop material;
after the thinning, selectively eliminating the first etch stop material to a bottom portion of the second etch stop material; and
after the eliminating, removing a bottom portion of the semiconductor wafer.

2. The method of claim 1 , wherein the etch stop trench is formed in an isolation region of the semiconductor wafer.

3. The method of claim 2 , wherein the second etch stop material comprises an electrically insulating material that electrically isolates the active device from another active device in the device layer.

4. The method of claim 2 , further comprising:
after the producing, forming electrically insulating material in the isolation region to electrically isolate the active device from another active device in the device layer.

5. The method of claim 2 , wherein the isolation region extends a first depth below a top surface of the semiconductor wafer, and the forming comprises recessing the first etch stop material below the top surface of the semiconductor wafer to a second depth that is less than the first depth.

6. The method of claim 1 , wherein the second etch stop material is a dielectric material in an active device layer formed in the top portion of the semiconductor wafer.

7. The method of claim 1 , wherein the thinning comprises at least two selected from the group consisting of mechanical grinding, chemical mechanical polishing, and wet etching.

8. The method of claim 1 , wherein the selectively eliminating comprises selectively etching the first etch stop material with an etchant that etches the first etch stop material at a higher rate than the semiconductor wafer.

9. The method of claim 1 , wherein the removing comprises chemical mechanical polishing the bottom portion of the semiconductor wafer.

10. The method of claim 1 , wherein the fabricating is performed after the second etch stop material is produced on the first etch stop material.

11. The method of claim 10 , wherein the fabricating is performed before the semiconductor wafer is bonded to the handle wafer.

12. The method of claim 1 , further comprising constructing one or more dielectric layers and one or more metallization layers on the device layer.

13. The method of claim 12 , wherein the fabricating comprises fabricating multiple active devices on the top portion of the semiconductor wafer, and at least one of the one or more metallization layers interconnects respective ones of the active devices.

14. The method of claim 1 , wherein the creating comprises creating multiple etch stop trenches in the top portion of the semiconductor wafer, and the forming and the producing are respectively performed with respect to each of the one or more etch stop trenches.

15. The method of claim 1 , wherein the semiconductor wafer is a bulk semiconductor wafer.

16. The method of claim 1 , wherein the semiconductor wafer is a bulk silicon wafer.

17. The method of claim 1 , wherein the creating comprises creating the etch stop trench with a depth of 1-2 micrometers below a top surface of the semiconductor wafer.

18. The method of claim 1 , wherein:
after the removing, the semiconductor wafer has a thickness less than 140 nanometers where the bottom portion of the semiconductor wafer is removed.

19. The method of claim 1 , wherein:
after the removing, the semiconductor wafer has a thickness less than 10 nanometers where the bottom portion of the semiconductor wafer is removed.

20. The method of claim 1 , further comprising:
after the removing, forming an insulator layer on a bottom surface of the semiconductor wafer and smoothing the insulator layer;
wherein, after the smoothing, the insulator layer has a bottom surface characterized by a surface variation of less than 5 micrometers.

21. A semiconductor structure, comprising:
a bulk semiconductor wafer comprising a bottom surface, a top surface, and isolation regions filled with electrically insulating material extending from the bottom surface to the top surface, wherein at least one region of the bulk semiconductor wafer is less than 140 nanometers thick;
a device layer comprising active devices on the bulk semiconductor wafer, wherein isolation regions electrically isolate respective ones of the active devices from one another; one or more dielectric layers and one or more metallization layers on the device layer; and
an oxide layer on the bottom surface of the bulk semiconductor wafer, wherein the oxide layer has a bottom surface characterized by a surface variation of less than 5 micrometers, wherein each of the isolation regions comprises a shallow trench isolation region extending to a first depth and an insulator region within the shallow trench isolation region extending to a second depth less than the first depth, further wherein the oxide layer contacts the insulator region.

22. The semiconductor structure of claim 21 , wherein the at least one region of the bulk semiconductor wafer is less than 10 nanometers thick.

Assignees

• Qualcomm Inc

Inventors

• Goktepeli Sinan

Classifications

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/642 Primary

  Chemical etching · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W74/014

  using batch processing · CPC title