Method for manufacture of fine line circuitry

Patent metadata

Field	Value
Publication number	US-9713266-B2
Application number	US-201314373961-A
Country	US
Kind code	B2
Filing date	Feb 6, 2013
Priority date	Mar 29, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

The present invention relates to a method for manufacture of fine line circuitry in the manufacture of printed circuit boards, IC substrates and the like. The method utilizes a first conductive layer on the smooth surface of a build-up layer and a second conductive layer selected from electrically conductive polymers, colloidal noble metals and electrically conductive carbon particles on the roughened walls of at least one opening which are formed after depositing the first conductive layer.

First claim

The invention claimed is:

1. A method for manufacture of fine line circuitry comprising, in the following order, the steps of
(i) providing a dielectric build-up layer having a front side surface area and a back side surface area and wherein at least a portion of the back side surface area comprises at least one copper area and wherein a dielectric layer is attached to said back side surface area and wherein an adhesion promoting layer consisting of organosilane compounds is attached to the front side surface area of the build-up layer, wherein the adhesion promoting layer is formed by
(a) treating said front side surface area with a solution comprising at least one organosilane compound to form the adhesion promoting layer consisting of the organosilane compounds, and
(b) treating said adhesion promoting layer consisting of the organosilane compounds with a solution comprising an oxidizing agent,
(ii) depositing a first conductive layer onto the adhesion promoting layer,
(iii) forming at least one opening which extends through the first conductive layer, the adhesion promoting layer and the build-up layer to the at least one copper area,
(iv) cleaning the dielectric side walls and the copper area of the at least one opening to obtain cleaned side walls and a cleaned copper area,
(v) forming a second conductive layer only on the cleaned side walls wherein the second conductive layer is selected from the group consisting of electrically conductive polymers, colloidal particles comprising a noble metal, and electrically conductive carbon particles,
(vi) applying a resist layer onto the first conductive layer; and patterning said resist layer,
(vii) depositing a copper layer by electroplating into the at least one opening of the patterned resist layer,
(viii) removing the patterned resist layer and
(ix) removing those portions of the first conductive layer which are not covered by the electroplated copper layer.

2. The method for manufacture of fine line circuitry according to claim 1 wherein the at least one organosilane compound is represented by the formula
A (4-x) SiB x

wherein
each A is a hydrolyzable group,
x is 1 to 3, and
each B is independently selected from the group consisting of C 1 -C 20 alkyl, aryl, amino aryl and a functional group represented by the formula
C n H 2n X,

wherein
n is from 0 to 15, and
X is selected from the group consisting of amino, amido, hydroxy, alkoxy, halo, mercapto, carboxy, carboxy ester, carboxamide, thiocarboxamide, acyl, vinyl, allyl, styryl, epoxy, epoxycyclohexyl, glycidoxy, isocyanato, thiocyanato, thioisocyanato, ureido, thioureido, guanidino, thioglycidoxy, acryloxy, methacryloxy groups, carboxy ester, and Si(OR) 3 , and wherein R is a C 1 -C 5 alkyl group.

3. The method for manufacture of fine line circuitry according to claim 2 wherein the hydrolyzable group A is selected from the group consisting of —OH, —OR 2 and wherein R 2 is selected from the group consisting of C 1 -C 5 alkyl and —OCOR 3 and wherein R 3 is H or a C 1 -C 5 alkyl group.

4. The method for manufacture of fine line circuitry according to claim 1 wherein the oxidizing agent is an alkaline aqueous solution of permanganate ions.

5. The method for manufacture of fine line circuitry according to claim 1 wherein the first conductive layer comprises copper deposited by electroless plating.

6. The method for manufacture of fine line circuitry according to claim 1 wherein the at least one opening is formed by laser drilling.

7. The method for manufacture of fine line circuitry according to claim 1 wherein the dielectric side walls and the copper area of the at least one opening are cleaned by a desmear method.

8. The method for manufacture of fine line circuitry according to claim 1 wherein the second conductive layer comprises an electrically conductive polymer which is selected from the group consisting of polythiophene, polypyrrole, polyaniline, derivatives and mixtures thereof.

9. The method for manufacture of fine line circuitry according to claim 1 wherein the second conductive layer in step (v) is formed by
(v) a) bringing the cleaned side walls of the at least one opening into contact with a solution of a water-soluble polymer,
(v) b) treating the cleaned side walls of the at least one opening with a permanganate solution and
(v) c) treating the cleaned side walls of the at least one opening with an acidic aqueous solution or an acidic microemulsion of aqueous base containing at least one thiophene compound and at least one sulfonic acid.

10. The method for manufacture of fine line circuitry according to claim 9 wherein the water-soluble polymer is selected from the group consisting of polyvinyl amine, polyethylene imine, polyvinyl imidazole, alkylamine ethylene oxide copolymers, polyethylene glycol, polypropylene glycol, copolymers of ethylene glycol and polypropylene glycol, polyvinyl alcohol, polyacrylates, polyacrylamide, polyvinylpyrrolidone and mixtures thereof.

11. The method for manufacture of fine line circuitry according to claim 9 wherein the at least one thiophene compound is selected from the group consisting of 3-heterosubstituted thiophenes and 3,4-heterosubstituted thiophenes.

12. The method for manufacture of fine line circuitry according to claim 10 wherein the at least one thiophene compound is selected from the group consisting of 3-heterosubstituted thiophenes and 3,4-heterosubstituted thiophenes.

13. The method for manufacture of fine line circuitry according to claim 9 wherein the at least one sulfonic acid is selected from the group comprising methane sulfonic acid, ethane sulfonic acid, methane disulfonic acid, ethane dilsulfonic acid, naphthalene-1-5-disulfonic acid, dodecylbenzenesulfonic acid, polystyrenesulfonic acid and mixtures thereof.

14. The method for manufacture of fine line circuitry according to claim 10 wherein the at least one sulfonic acid is selected from the group comprising methane sulfonic acid, ethane sulfonic acid, methane disulfonic acid, ethane dilsulfonic acid, naphthalene-1-5-disulfonic acid, dodecylbenzenesulfonic acid, polystyrenesulfonic acid and mixtures thereof.

15. The method for manufacture of fine line circuitry according to claim 11 wherein the at least one sulfonic acid is selected from the group comprising methane sulfonic acid, ethane sulfonic acid, methane disulfonic acid, ethane dilsulfonic acid, naphthalene-1-5-disulfonic acid, dodecylbenzenesulfonic acid, polystyrenesulfonic acid and mixtures thereof.

16. The method for manufacture of fine line circuitry according claim 9 wherein the pH value of the solution comprising at least one thiophene compound and at least on sulfonic acid ranges from 0 to 3.

17. The method for manufacture of fine line circuitry according claim 10 wherein the pH value of the solution comprising at least one thiophene compound and at least on sulfonic acid ranges from 0 to 3.

18. The method for manufacture of fine line circuitry according claim 11 wherein the pH value of the solution comprising at least one thiophene compound and at least on sulfonic acid ranges from 0 to 3.

19. The method for manufacture of fine line circuitry according claim 12 wherein the pH value of the solution comprising at least one thiophene compound and at least on sulfonic acid ranges from 0 to 3.

20. The method for manufacture of fine line circuitry according claim 13 wherein the pH value of the solution comprising at least one thiophene compound and at least on sulfoni

Assignees

• Atotech Deutschland Gmbh

Inventors

• Nichols Richard
• Jang Don
• Riebel Harald
• Brüning Frank

Classifications

• C25D3/38

  of copper · CPC title

• H05K3/381

  by special treatment of the substrate · CPC title

• H05K3/389

  by the use of a coupling agent, e.g. silane · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• C23C18/1653

  Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating · CPC title