Manufacturing a package using plateable encapsulant

US2019341324A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019341324-A1
Application numberUS-201916514853-A
CountryUS
Kind codeA1
Filing dateJul 17, 2019
Priority dateMar 3, 2016
Publication dateNov 7, 2019
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of manufacturing a package, the method comprising: embedding a semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material. 2 . The Method according to claim 1 , further comprising electrically coupling of a redistribution layer with the semiconductor chip. 3 . The Method according to claim 2 , wherein the redistribution layer and the semiconductor chip are electrically coupled for providing an electrical conductive coupling to the redistribution layer and an electronic periphery, that is at least partially localized at an surface of the package. 4 . The Method according to claim 1 , wherein the encapsulant is a mold compound. 5 . The Method according to claim 1 , wherein the plating comprises a plating of an outer lateral sidewall of the converted part of the encapsulant with an electrically conductive material. 6 . The Method according to claim 1 , wherein the sidewall of the encapsulant is exposed before the plating, in particular is exposed by sawing, while the encapsulant of the package is arranged on a temporary carrier. 7 . The Method according to claim 1 , wherein the selectively converting of a part of the transition metal comprises a laser treatment. 8 . The Method according to claim 1 , wherein the selectively converting of a part of the transition metal comprises a chemical reduction. 9 . The Method according to claim 1 , wherein the plating is an electroless plating. 10 . The Method according to claim 1 , wherein the transition metal is selected from one of the group consisting of palladium, nickel and copper. 11 . The Method according to claim 1 , wherein the semiconductor chip is a power semiconductor chip. 12 . The Method according to claim 1 , wherein the external periphery comprises a at least one of a printed circuit board, an antenna structure, a wiring connections for such an antenna structure, an EMI shielding structures and a passive component. 13 . The Method according to claim 1 , coupling a complexing agent to the transition metal, in particular configured to enhance a chemical stearic effect to maintain an electrically insulating behaviour of the transition metal in a bulk mold compound. 14 . The Method according to claim 1 , wherein the encapsulant comprises a polymer cluster and a coupling agent between the transition metal and the polymer cluster. 15 . The Method according to claim 14 , wherein the polymer cluster comprises at least one material of a group consisting of a wax, an adhesion promoter, a mold compound catalyst, and a coupling agent for silica. 16 . The Method according to claim 14 , wherein the polymer cluster comprises at least one rest, in particular at least one of a hydrophobic group, and a hydrophilic group. 17 . The Method according to claim 14 , the method further comprising removing a surface portion of the polymer cluster to thereby expose the transition metal; activating the exposed transition metal. 18 . A package, comprising: at least one semiconductor chip; and an encapsulant in which the semiconductor chip is embedded; wherein the encapsulant comprises a transition metal in a concentration in a range between 10 ppm and 10,000 ppm, wherein a part of the transition metal is selectively converted, such that the electrical conductivity of the encapsulant is increased, wherein the converted part of the encapsulant is plated with an electrically conductive material.

Assignees

Inventors

Classifications

  • shielding resins · CPC title

  • the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

  • characterised by their shape or disposition · CPC title

  • batch processes · CPC title

  • changes in materials · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2019341324A1 cover?
A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conducti…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10W74/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).