Image sensor devices including a superlattice

US12575199B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12575199-B2
Application numberUS-202318192371-A
CountryUS
Kind codeB2
Filing dateMar 29, 2023
Priority dateAug 23, 2022
Publication dateMar 10, 2026
Grant dateMar 10, 2026

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Abstract

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An image sensor device may include a semiconductor substrate, a pixel region within the semiconductor substrate comprising a first dopant having a first conductivity type, a first pinning layer on a surface of the substrate and including a second dopant having a second conductivity type different the first conductivity type, and a second pinning layer in the semiconductor substrate adjacent at least one side of the pixel region and including a superlattice and the second dopant. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

First claim

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The invention claimed is: 1 . An image sensor device comprising: a semiconductor substrate; a pixel region within the semiconductor substrate comprising a first dopant having a first conductivity type; a first pinning layer on a surface of the substrate and comprising a second dopant having a second conductivity type different than the first conductivity type; and a second pinning layer in the semiconductor substrate adjacent at least one side of the pixel region and comprising a superlattice and the second dopant, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. 2 . The image sensor device of claim 1 wherein the second pinning layer extends along opposite sides of the pixel region. 3 . The image sensor device of claim 2 wherein the second pinning layer extends along a bottom of the pixel region. 4 . The image sensor device of claim 1 further comprising an isolation region in the semiconductor substrate adjacent the second pinning layer. 5 . The image sensor device of claim 4 wherein the second pinning layer wraps around the isolation region. 6 . The image sensor device of claim 1 wherein the first pinning layer is adjacent a first end of the pixel region; and further comprising a color filter layer on the substrate adjacent a second end of the pixel region opposite the first end. 7 . The image sensor device of claim 6 further comprising a lens on the color filter layer. 8 . The image sensor device of claim 1 further comprising a transfer gate adjacent the first pinning layer, a conductive contact spaced apart from the transfer gate, and a conductive via extending between the transfer gate and the conductive contact. 9 . The image sensor device of claim 1 wherein the second pinning layer further comprises fluorine. 10 . The image sensor device of claim 1 wherein the base semiconductor portion comprises silicon. 11 . The image sensor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen. 12 . The image sensor device of claim 1 wherein the pixel region comprises a doped region including the first dopant, and an intrinsic region between the doped region and the second pinning layer. 13 . The image sensor device of claim 12 wherein the superlattice comprises a first superlattice; and further comprising a second superlattice in the intrinsic portion, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. 14 . The image sesnor device of claim 13 wherein the second superlattice at least partially surrounds the doped region. 15 . An image sensor device comprising: a semiconductor substrate; a pixel region within the semiconductor substrate comprising a first dopant having a first conductivity type; a first pinning layer on a surface of the substrate and comprising a second dopant having a second conductivity type different than the first conductivity type; a second pinning layer in the semiconductor substrate adjacent at least one side of the pixel region and comprising a superlattice and the second dopant, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and an isolation region in the semiconductor substrate adjacent the second pinning layer. 16 . The image sensor device of claim 15 wherein the second pinning layer extends along opposite sides and a bottom of the pixel region. 17 . The image sensor device of claim 15 wherein the second pinning layer wraps around the isolation region. 18 . The image sensor device of claim 15 wherein the first pinning layer is adjacent a first end of the pixel region; and further comprising a color filter layer on the substrate adjacent a second end of the pixel region opposite the first end, and a lens on the color filter layer. 19 . The image sensor device of claim 15 further comprising a transfer gate adjacent the first pinning layer, a conductive contact spaced apart from the transfer gate, and a conductive via extending between the transfer gate and the conductive contact. 20 . The image sensor device of claim 15 wherein the second pinning layer further comprises fluorine. 21 . An image sensor device comprising: a semiconductor substrate; a pixel region within the semiconductor substrate comprising a first dopant having a first conductivity type; a first pinning layer on a surface of the substrate and comprising a second dopant having a second conductivity type different than the first conductivity type; and a second pinning layer in the semiconductor substrate adjacent at least one side of the pixel region and comprising a superlattice and the second dopant, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. 22 . The image sensor device of claim 21 wherein the second pinning layer extends along opposite sides and a bottom of the pixel region. 23 . The image sensor device of claim 21 further comprising an isolation region in the semiconductor substrate adjacent the second pinning layer; and wherein the second pinning layer wraps around the isolation region. 24 . The image sensor device of claim 21 wherein the first pinning layer is adjacent a first end of the pixel region; and further comprising a color filter layer on the substrate adjacent a second end of the pixel region opposite the first end, and a lens on the color filter layer. 25 . The image sensor device of claim 21 further comprising a transfer gate adjacent the first pinning layer, a conductive contact spaced apart from the transfer gate, and a conductive via extending between the transfer gate and the conductive contact. 26 . The image sensor device of claim 21 wherein the second pinning layer further comprises fluorine.

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What does patent US12575199B2 cover?
An image sensor device may include a semiconductor substrate, a pixel region within the semiconductor substrate comprising a first dopant having a first conductivity type, a first pinning layer on a surface of the substrate and including a second dopant having a second conductivity type different the first conductivity type, and a second pinning layer in the semiconductor substrate adjacent at …
Who is the assignee on this patent?
Atomera Inc
What technology area does this patent fall under?
Primary CPC classification H10F39/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).