Single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET

Patent metadata

Field	Value
Publication number	US-12568683-B2
Application number	US-202217808360-A
Country	US
Kind code	B2
Filing date	Jun 23, 2022
Priority date	Jun 23, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET. A PFET comprising at least one silicon germanium channel is formed. An NFET comprising at least one silicon channel is formed, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction.

First claim

What is claimed is:

1 . A device comprising:
a p-type field-effect transistor (PFET) comprising at least one silicon germanium channel and a first punch-through-stopper-implant layer; and an n-type field-effect transistor (NFET) comprising at least one silicon channel, a second punch-through-stopper implant layer, and an electrically insulating bottom isolation layer disposed between the at least one silicon channel and the second punch-through-stopper implant layer, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction; wherein the first punch-through-stopper-implant layer facilitates compressive strain to the at least one silicon germanium channel; wherein a first top surface of the first punch-through-stopper-implant layer is coplanar with a second top surface of the second punch-through-stopper implant layer.

2 . The device of claim 1 , wherein the PFET is free of the electrically bottom isolation layer.

3 . The device of claim 1 , wherein the PFET comprises a p-type gate stack, a portion of the p-type gate stack extending vertically below a top surface of an electrically insulating bottom isolation layer.

4 . The device of claim 1 , wherein:
the PFET comprises a plurality of silicon germanium channels one of which is the at least one silicon germanium channel, the NFET comprising a plurality of silicon channels one of which is the at least one silicon channel; and the plurality of silicon germanium channels and the plurality of silicon channels are staggered in the vertical direction.

5 . The device of claim 1 , wherein inner spacers of the PFET are staggered in the vertical direction from inner spacers of the NFET.

6 . The device of claim 1 , wherein a center axis of epitaxial material of a source and a drain of the PFET is below a center axis of epitaxial material of a source and a drain of the NFET.

7 . The device of claim 1 , wherein a center axis of the at least one silicon channel is offset in the vertical direction from a center axis of the at least one silicon germanium channel.

8 . The device of claim 1 , wherein an electrically insulating bottom isolation layer in the NFET causes a center axis of the at least one silicon channel to be offset in the vertical direction from a center axis of the at least one silicon germanium channel.

9 . The device of claim 1 , wherein at least one portion of the first punch-through-stopper-implant layer is recessed.

10 . The device of claim 1 , wherein:
epitaxial material of a source and a drain in the PFET and the NFET comprises a composite material; the epitaxial material of the source and the drain in the PFET is in contact with the first punch-through-stopper implant layer; and a crystal lattice of the at least one silicon germanium channel comprises the compressive strain generated by a compressive force from the epitaxial material of the source and the drain in the PFET.

11 . The device of claim 1 , wherein a top surface of a work function material stack for the NFET is above a top surface of a work function material stack for the PFET.

12 . A method comprising:
forming a PFET comprising at least one silicon germanium channel and a first punch-through-stopper-implant layer; and forming an NFET comprising at least one silicon channel, a second punch-through-stopper implant layer, and an electrically insulating bottom isolation layer disposed between the at least one silicon channel and the second punch-through-stopper implant layer, the PFET being positioned laterally to the NFET, the at least one silicon channel and the at least one silicon germanium channel being staggered in a vertical direction; wherein the first punch-through-stopper-implant layer facilitates compressive strain to the at least one silicon germanium channel; wherein a first top surface of the first punch-through-stopper-implant layer is coplanar with a second top surface of the second punch-through-stopper implant layer.

13 . The method of claim 12 , wherein the PFET is free of the electrically bottom isolation layer.

14 . The method of claim 12 , wherein the PFET comprises a p-type gate stack, a portion of the p-type gate stack extending vertically below a top surface of an electrically insulating bottom isolation layer.

15 . The method of claim 12 , wherein:
the PFET comprises a plurality of silicon germanium channels one of which is the at least one silicon germanium channel, the NFET comprising a plurality of silicon channels one of which is the at least one silicon channel; and the plurality of silicon germanium channels and the plurality of silicon channels are staggered in the vertical direction.

16 . The method of claim 12 , wherein inner spacers of the PFET are staggered in the vertical direction from inner spacers of the NFET.

17 . The method of claim 12 , wherein a center axis of epitaxial material of a source and a drain of the PFET is below a center axis of epitaxial material of a source and a drain of the NFET.

Assignees

• IBM

Inventors

• Frougier Julien
• Greene Andrew M
• Mochizuki Shogo
• Cheng Kangguo
• Xie Ruilong
• Wu Heng
• Sung Min Gyu
• Qin Liqiao
• Tsutsui Gen

Classifications

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10D84/851

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D84/832

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D30/504

  wherein the stacked channels have different properties · CPC title

• H10D30/502

  characterised by the stacked channels · CPC title