Isolation manufacturing method for semiconductor structures

Patent metadata

Field	Value
Publication number	US-11037835-B2
Application number	US-201916392189-A
Country	US
Kind code	B2
Filing date	Apr 23, 2019
Priority date	Jun 20, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material.

First claim

What is claimed is:

1. A method, comprising:
providing a semiconductor structure that includes a semiconductor substrate and a first semiconductor material extending from a first region to a second region over the semiconductor substrate, wherein the semiconductor substrate and the first semiconductor material have different crystalline orientations in both the first region and the second region, wherein the semiconductor structure includes a dielectric layer stacked between the semiconductor substrate and the first semiconductor material;
removing a portion of the first semiconductor material in the second region to form a recess, the recess exposing a sidewall of the first semiconductor material disposed in the first region, wherein the removing of the portion of the first semiconductor material also includes removing a portion of the dielectric layer to expose a top surface of the semiconductor substrate in the second region;
forming a dielectric material covering the sidewall; and
while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material, wherein the semiconductor substrate and the second semiconductor material have the same crystalline orientation.

2. The method of claim 1 , wherein the forming of the dielectric includes:
depositing the dielectric material covering the semiconductor structure in the first and second regions; and
removing a portion of the dielectric material from the second region, wherein another portion of the dielectric material covering the sidewall and a top surface of the first semiconductor material in the first region remains.

3. The method of claim 1 , wherein the removing of the portion of the first semiconductor material includes:
forming a mask covering the first semiconductor material in the first region; and
etching the first semiconductor material in the second region to form the recess and expose a top surface of the semiconductor substrate in the second region.

4. The method of claim 1 , wherein:
the first semiconductor material is in a first crystalline structure with a top surface on a (110) crystal plane; and
the second semiconductor material is in a second crystalline structure with a top surface on a (100) crystal plane.

5. The method of claim 1 , wherein:
the first semiconductor material includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, the first and second semiconductor layers having different material compositions; and
the second semiconductor material includes a plurality of third semiconductor layers interleaved with a plurality of fourth semiconductor layers, the third and fourth semiconductor layers having different material compositions.

6. The method of claim 1 , wherein:
the first semiconductor material includes a material composition uniformly throughout the first semiconductor material; and
the second semiconductor material includes a plurality of third semiconductor layers interleaved with a plurality of fourth semiconductor layers, the third and fourth semiconductor layers having different material compositions.

7. The method of claim 1 , wherein a bottom surface of the second semiconductor material is below a bottom surface of the dielectric layer.

8. The method of claim 1 , wherein a bottom surface of the second semiconductor material is below a bottom surface of the first semiconductor material.

9. The method of claim 1 , further includes:
patterning the first and second semiconductor materials to form a first fin in the first region and a second fin in the second region.

10. A method of forming a semiconductor device, comprising:
providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate, the first semiconductor layers having a different material composition than the second semiconductor layers and the first and second semiconductor layers being alternatingly disposed with respect to each other in a vertical direction;
etching a portion of the pluralities of first and second semiconductor layers such that a sidewall of the pluralities of first and second semiconductor layers and a top surface of the substrate are exposed;
depositing a dielectric material layer over the sidewall; and
while the dielectric material layer is disposed on the sidewall, epitaxially growing a plurality of third semiconductor layers and a plurality of fourth semiconductor layers from the exposed top surface of the substrate, the dielectric material layer separating the plurality of third and fourth semiconductor layers from contacting the plurality of first and second semiconductor layers, the plurality of third semiconductor layers having a different material composition than the plurality of fourth semiconductor layers and the pluralities of third and fourth semiconductor layers being alternatingly disposed with respect to each other in the vertical direction, wherein a bottommost portion of the pluralities of third and fourth semiconductor layers is lower than a bottommost portion of the pluralities of first and second semiconductor layers.

11. The method of claim 10 , wherein a bottommost portion of the dielectric material layer is below the bottommost portion of the pluralities of first and second semiconductor layers.

12. The method of claim 10 , wherein each of the first, second, third, and fourth semiconductor layers has the same crystalline orientation.

13. The method of claim 10 , wherein the first and second semiconductor layers have a first crystalline orientation, and the third and fourth semiconductor layers have a second crystalline orientation different from the first crystalline orientation.

14. The method of claim 10 , wherein the first and second semiconductor layers are in a first crystalline structure with a first crystal direction of <110>, and the third and fourth semiconductor layers are in a second crystalline structure with a second crystal direction of <110>that is offset from the first crystal direction of <110>.

15. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region; a first semiconductor structure disposed over the semiconductor substrate within the first region, the first semiconductor structure being operable as a first channel for conducting currents between first source/drain (S/D) features;
a dielectric layer stacked between the semiconductor substrate and the first semiconductor structure, wherein the dielectric layer separates the semiconductor substrate from contacting the first semiconductor structure, wherein a bottom surface of the first semiconductor structure is directly above a top surface of the dielectric layer; and
a second semiconductor structure disposed over the semiconductor substrate within the second region, the second semiconductor structure being operable as a second channel for conducting currents between second S/D features,
wherein the first and second semiconductor structures have different crystalline orientations; and
wherein a bottom surface of the second semiconductor structure is below a bottom surface of the dielectric layer.

16. The semiconductor structure of claim 15 , wherein the dielectric layer is in physical contact with both the semiconductor substrate and the first semiconductor structure.

17. The semiconductor structure of claim 15 , wherein the second semiconductor structure and the semiconductor substrate have the same crystalline orientation.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen I-Sheng
• Chen Tzu-Chiang
• Chang Chih-Sheng
• Wu Cheng-Hsien

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title