Vertically stacked dual channel nanosheet devices

Patent metadata

Field	Value
Publication number	US-10553678-B2
Application number	US-201715802021-A
Country	US
Kind code	B2
Filing date	Nov 2, 2017
Priority date	Nov 2, 2017
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a pFET device comprising a first functional gate structure present on physically exposed surfaces, and between, each SiGe channel material nanosheet of a vertical stack of suspended SiGe channel material nanosheets;
an nFET device stacked vertically above the pFET device and comprising a second functional gate structure present on physically exposed surfaces, and between, each Si channel material nanosheet of a vertical stack of suspended Si channel material nanosheets, wherein the first and second functional gate structures comprise a same work function metal;
a Si channel material extension region located at each end of each Si channel material nanosheet: and
a SiGe channel material extension region located at each end of each SiGe channel material nanosheet, wherein each Si channel material extension region has a thickness that is greater than a thickness of each Si channel material nanosheet, and each SiGe channel material extension region has a germanium content that is less than a germanium content of each SiGe channel material nanosheet.

2. The semiconductor structure of claim 1 , further comprising pFET S/D regions present on physically exposed sidewalls of each SiGe channel material extension region, and nFET S/D regions present on physically exposed sidewalls of each Si channel material extension region.

3. The semiconductor structure of claim 2 , further comprising a dielectric material located between each pFET S/D region and each nFET S/D region.

4. The semiconductor structure of claim 2 , further comprising a shared S/D contact structure located on a first side of the vertically stacked nFET and pFET devices, wherein the shared S/D contact structure passes through one of the nFET S/D regions and into one of the pFET S/D regions.

5. The semiconductor structure of claim 4 , further comprising an nFET S/D contact structure and a pFET S/D contact structure located on a second side of the vertically stacked nFET and pFET devices, opposite the first side, wherein the nFET S/D contact structure is present in another of the nFET S/D regions and the pFET contact structure is present in another of the pFET S/D regions.

6. The semiconductor structure of claim 5 , wherein the nFET S/D contact structure is separated from the pFET S/D contact structure by a dielectric material.

7. The semiconductor structure of claim 1 , wherein the same work function metal comprises an n-type work function metal.

8. The semiconductor structure of claim 1 , wherein the same work function metal comprises a p-type work function metal.

9. The semiconductor structure of claim 1 , further comprising a dielectric isolation layer located beneath the pFET device, the dielectric isolation layer is located on a surface of a semiconductor substrate.

10. A semiconductor structure comprising:
a pFET device comprising a first functional gate structure present on physically exposed surfaces, and between, each SiGe channel material nanosheet of a vertical stack of suspended SiGe channel material nanosheets, wherein a SiGe channel material extension region is located at each end of each SiGe channel material nanosheet;
an nFET device stacked vertically above the pFET device and comprising a second functional gate structure present on physically exposed surfaces, and between, each Si channel material nanosheet of a vertical stack of suspended Si channel material nanosheets, wherein a Si channel material extension region is located at each end of each Si channel material nanosheet, and the first and second functional gate structures comprise a same work function metal;
pFET S/D regions present on physically exposed sidewalls of each SiGe channel material extension region;
nFET S/D regions present on physically exposed sidewalls of each Si channel material extension region;
a shared S/D contact structure located on a first side of the vertically stacked nFET and pFET devices, wherein the shared S/D contact structure passes through one of the nFET S/D regions and into one of the pFET S/D regions; and
an nFET S/D contact structure and a pFET S/D contact structure located on a second side of the vertically stacked nFET and pFET devices, opposite the first side, wherein the nFET S/D contact structure is present in another of the nFET S/D regions and the pFET contact structure is present in another of the pFET S/D regions.

Assignees

• IBM

Inventors

• Lee Choonghyun
• Zhang Jingyun
• Hashemi Pouya
• Ando Takashi
• Reznicek Alexander

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title