Buffer regions for blocking unwanted diffusion in nanosheet transistors

Patent metadata

Field	Value
Publication number	US-10263100-B1
Application number	US-201815924799-A
Country	US
Kind code	B1
Filing date	Mar 19, 2018
Priority date	Mar 19, 2018
Publication date	Apr 16, 2019
Grant date	Apr 16, 2019

Abstract

Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device. The fabrication operations include forming a sacrificial nanosheet and a channel nanosheet over a substrate, forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet, wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistor device, wherein the fabrication operations include:
forming a sacrificial nanosheet and a channel nanosheet over a substrate; and
forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet;
wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer.

2. The method of claim 1 , wherein a thickness of the diffusion barrier layer is selected to substantially prevent the predetermined semiconductor material from diffusing through the diffusion barrier layer.

3. The method of claim 2 , wherein the diffusion barrier layer comprises a rare earth oxide.

4. The method of claim 1 , wherein the diffusion barrier layer comprises a single crystalline diffusion barrier material.

5. The method of claim 4 , wherein:
the sacrificial nanosheet comprise a single crystalline first semiconductor material; and
the channel nanosheet comprises a single crystalline second semiconductor material.

6. The method of claim 5 , wherein the fabrication operations further include:
epitaxially growing the diffusion barrier layer over channel nanosheet; and
epitaxially growing the sacrificial nanosheet over the diffusion barrier layer.

7. The method of claim 5 , wherein the fabrication operations further include:
epitaxially growing the diffusion barrier layer over sacrificial nanosheet; and
epitaxially growing the channel nanosheet over the diffusion barrier layer.

8. The method of claim 1 , wherein:
the channel nanosheet comprises silicon;
the sacrificial nanosheet comprises silicon germanium; and
the predetermined semiconductor material comprises germanium.

9. The method of claim 1 , wherein:
the channel nanosheet comprises silicon germanium;
the sacrificial nanosheet comprises silicon; and
the predetermined semiconductor material comprises germanium.

10. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistor device, wherein the fabrication operations include:
forming a first diffusion barrier layer across from a major surface of a substrate;
forming a first nanosheet stack on an opposite side of the first diffusion barrier layer from the major surface of the substrate, wherein the first nanosheet stack comprises alternating channel nanosheets, stack diffusion barrier layers, and sacrificial nano sheets; and
forming the first nanosheet stack such that the stack diffusion barrier layers are positioned between the sacrificial nano sheets and the channel nanosheets;
wherein a diffusion coefficient of the stack diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the stack diffusion barrier layer.

11. The method of claim 10 , wherein a thickness of each of the stack diffusion barrier layers is selected to substantially prevent the predetermined semiconductor material from diffusing through each of the stack diffusion barrier layers.

12. The method of claim 11 , wherein the first diffusion barrier layer and the stack diffusion barrier layers comprise a rare earth oxide.

13. The method of claim 10 , wherein:
the first diffusion barrier layer and each of the stack diffusion barriers comprise a single crystalline diffusion barrier material;
each of the sacrificial nanosheets comprises a single crystalline first semiconductor material; and
each of the channel nano sheets comprises a single crystalline second semiconductor material.

14. The method of claim 13 , wherein the fabrication operations further include:
epitaxially growing the first nanosheet stack over the first diffusion barrier layer;
epitaxially growing the first nanosheet stack by epitaxially and alternately growing the alternating channel nanosheets, stack diffusion barrier layers, and sacrificial nano sheets.

15. The method of claim 10 , wherein:
the first diffusion barrier layer and each of the stack diffusion barrier layers comprise a rare earth oxide;
each channel nanosheet of the first nanosheet stack comprises silicon;
each sacrificial nanosheet of the first nanosheet stack comprises silicon germanium; and
the predetermined semiconductor material comprises germanium.

16. The method of claim 10 , wherein:
the first diffusion barrier layer and each of the stack diffusion barrier layers comprise a rare earth oxide;
each channel nanosheet of the first nanosheet stack comprises silicon germanium;
each sacrificial nanosheet of the first nanosheet stack comprises silicon; and
the predetermined semiconductor material comprises germanium.

17. The method of claim 14 , wherein the fabrication operations further include:
forming a second nanosheet stack on an opposite side of the first diffusion barrier layer from the major surface of the substrate, wherein the second nanosheet stack comprises alternating second channel nanosheets, second stack diffusion barrier layers, and second sacrificial nanosheets;
forming the second nanosheet stack such that the second stack diffusion barrier layers are positioned between the second sacrificial nanosheets and the second channel nanosheets;
wherein a diffusion coefficient of the second stack diffusion barrier layer is selected to substantially prevent a second predetermined semiconductor material from diffusing through the second stack diffusion barrier layer;
wherein the second diffusion barrier layer and each of the second stack diffusion barriers comprise the single crystalline diffusion barrier material;
wherein each of the second sacrificial nanosheets comprises a single crystalline third semiconductor material;
wherein each of the second channel nanosheets comprises a single crystalline fourth semiconductor material;
epitaxially growing the second nanosheet stack over the first diffusion barrier layer; and
epitaxially growing the second nanosheet stack by epitaxially and alternately growing the alternating second channel nanosheets, second stack diffusion barrier layers, and second sacrificial nanosheets;
wherein the first diffusion barrier layer, the second diffusion barrier layer, each of the stack diffusion barrier layers, and each of the second stack diffusion barrier layers comprise a rare earth oxide;
wherein each channel nanosheet of the first nanosheet stack comprises silicon;
wherein each sacrificial nanosheet of the first nanosheet stack comprises silicon germanium;
wherein each channel nanosheet of the second nanosheet stack comprises silicon germanium;
wherein each sacrificial nanosheet of the second nanosheet stack comprises silicon;
wherein the predetermined semiconductor material comprises germanium.

18. The method of claim 11 , wherein the fabrication operations further include:
performing inner spacer fabrication operations that include:
replacing an end region of a selected one of the stack diffusion barrier layers of the first nanosheet stack with an inner spacer material end region;
wherein an inner spacer of the nanosheet field effect transistor comprises:
a central inner spacer body comprising the inner spacer material end region;

a top inner spacer region comprising an end region of a first one of the stack diffusion barrier layers; and
a bottom inner spacer region comprising an end region

Assignees

• IBM

Inventors

• Bi Zhenxing
• Cheng Kangguo
• Li Juntao
• Xu Peng

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title