Semiconductor device

Patent metadata

Field	Value
Publication number	US-12568628-B2
Application number	US-202118024823-A
Country	US
Kind code	B2
Filing date	Sep 16, 2021
Priority date	Oct 2, 2020
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A memory device having large memory capacity is provided. A highly reliable memory device is provided. A semiconductor device includes a first conductive layer extending in a first direction, a structure body extending in a second direction intersecting with the first direction, a first insulating layer, and a second insulating layer. The structure body includes a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer. In an intersection portion of the first conductive layer and the structure body, the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order. The first insulating layer and the second insulating layer are stacked in the second direction. The functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer. The second conductive layer, the third insulating layer, and the semiconductor layer include a portion positioned inside a first opening provided in the first insulating layer and a portion positioned inside a second opening provided in the second insulating layer.

First claim

The invention claimed is:

1 . A semiconductor device comprising:
a first conductive layer extending in a first direction; a structure body extending in a second direction intersecting with the first direction; and a first insulating layer and a second insulating layer, wherein the structure body comprises a functional layer, a seventh insulating layer, a semiconductor layer, a third insulating layer, and a second conductive layer, wherein in an intersection portion of the first conductive layer and the structure body, the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order, wherein the first insulating layer and the second insulating layer are stacked in the second direction, wherein the seventh insulating layer, the functional layer, and the first conductive layer are placed between the first insulating layer and the second insulating layer, wherein the seventh insulating layer is provided in contact with a top surface, a bottom surface, and a side surface of the functional layer, wherein the seventh insulating layer comprises a portion in contact with the first conductive layer, and wherein the second conductive layer, the third insulating layer, and the semiconductor layer comprise a portion positioned inside a first opening provided in the first insulating layer and a portion positioned inside a second opening provided in the second insulating layer.

2 . A semiconductor device comprising:
a first conductive layer extending in a first direction; a structure body extending in a second direction intersecting with the first direction; and a first insulating layer and a second insulating layer, wherein the structure body comprises a functional layer, a third conductive layer, and a fourth insulating layer, wherein in an intersection portion of the first conductive layer and the structure body, the third conductive layer and the functional layer are placed concentrically around the fourth insulating layer in this order, wherein the first insulating layer and the second insulating layer are stacked in the second direction, wherein the functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer, wherein the functional layer comprises a portion in contact with the third conductive layer, and wherein the third conductive layer and the fourth insulating layer comprise a portion positioned inside a first opening provided in the first insulating layer and a portion positioned inside a second opening provided in the second insulating layer.

3 . A semiconductor device comprising:
a first conductive layer and a fourth conductive layer extending in a first direction; a structure body extending in a second direction intersecting with the first direction; and a first insulating layer, a second insulating layer, and a fifth insulating layer, wherein the structure body comprises a first portion and a second portion, wherein the first portion comprises a functional layer, a semiconductor layer, a third insulating layer, and a second conductive layer, wherein the second portion comprises a sixth insulating layer, the semiconductor layer, the third insulating layer, and the second conductive layer, wherein in an intersection portion of the first conductive layer, the fourth conductive layer, and the structure body,
the third insulating layer, the semiconductor layer, and the functional layer are placed concentrically around the second conductive layer in this order in the first portion; and
the third insulating layer, the semiconductor layer, and the sixth insulating layer are placed concentrically around the second conductive layer in this order in the second portion,
wherein the functional layer and the first conductive layer are placed between the first insulating layer and the second insulating layer, wherein the fourth conductive layer is placed between the second insulating layer and the fifth insulating layer, and wherein the second conductive layer, the third insulating layer, and the semiconductor layer comprise a portion positioned inside a first opening provided in the first insulating layer, a portion positioned inside a second opening provided in the second insulating layer, and a portion positioned inside a third opening provided in the fifth insulating layer.

4 . The semiconductor device according to claim 1 , further comprising an eighth insulating layer,
wherein the eighth insulating layer is placed between the semiconductor layer and the functional layer.

5 . The semiconductor device according to claim 4 ,
wherein the eighth insulating layer comprises silicon and nitrogen.

6 . The semiconductor device according to claim 1 ,
wherein the first direction is orthogonal to the second direction.

7 . The semiconductor device according to claim 1 ,
wherein the intersection portion functions as a memory cell.

8 . The semiconductor device according to claim 1 ,
wherein the semiconductor layer comprises at least one of indium and zinc.

9 . The semiconductor device according to claim 1 ,
wherein the functional layer exhibits ferroelectricity or anti-ferroelectricity.

10 . The semiconductor device according to claim 1 ,
wherein the functional layer comprises one or both of hafnium oxide and zirconium oxide.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Ikeda Takayuki
• Onuki tatsuya
• Kunitake Hitoshi
• Jinbo Yasuhiro

Classifications

• H10B53/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10B51/10

  characterised by the top-view layout · CPC title

• H10B51/20 Primary

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title