Vertical type memory device

Patent metadata

Field	Value
Publication number	US-9356044-B2
Application number	US-201514975703-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Oct 5, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a selection line extending in a first direction;
first and second vertically stacked memory cell strings arranged in a second direction crossing the first direction, the first and second vertically stacked memory cell strings commonly coupled to the same selection line;
first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;
a first sub-interconnection coupling the first vertically stacked memory cell string to the first bit line; and
a second sub-interconnection coupling the second vertically stacked memory cell string to the second bit line,
wherein the first sub-interconnection has a first protrusion protruding in the first direction, and
wherein the second sub-interconnection has a second protrusion protruding in a direction opposite to the first direction.

2. The device of claim 1 , wherein the selection line, the sub-interconnections, and the bit lines are sequentially provided on a substrate,
the vertically stacked memory cell strings are connected to the substrate,
the bit lines are provided on the vertically stacked memory cell strings, and
the sub-interconnections are provided between the vertically stacked memory cell strings and the bit lines.

3. The device of claim 1 , wherein each of the sub-interconnections has a longitudinal axis and a short axis,
a central part of the first sub-interconnection protrudes in the first direction along the short axis, and
a central part of the second sub-interconnection protrudes in the opposite direction to the first direction along the short axis.

4. The device of claim 3 , wherein the first sub-interconnection has a shorter length along the longitudinal axis than that of the second sub-interconnection.

5. The device of claim 1 , wherein the selection line comprises first, second and, third selection lines extending in the first direction, the selection lines spaced apart from each other in the second direction, and
wherein the device further comprises third and fourth vertically stacked memory cell strings arranged in the second direction, wherein the third vertically stacked memory cell string is coupled to the first selection line, the first and second vertically stacked memory cell strings are commonly coupled to the second selection line, and the fourth vertically stacked memory cell string is coupled to the third selection line.

6. The device of claim 5 , wherein the first sub-interconnection connects the first and third vertically stacked memory cell strings to the first bit line, and
the second sub-interconnection connects the third and fourth vertically stacked memory cell strings to the second bit line.

7. The device of claim 5 , wherein the first sub-interconnection is connected to the first bit line through the first protrusion, and the second sub-interconnection is connected to the second bit line through the second protrusion.

8. The device of claim 5 , further comprising:
a first separation insulating layer extending in the first direction, the first separation insulating layer provided between the first and second selection lines.

9. The device of claim 8 , wherein the first protrusion is vertically overlapped with the first separation insulating layer.

10. The device of claim 9 , further comprising:
a second separation insulating layer extending in the first direction, the separation insulating layer provided between the second and third selection lines, and
wherein the second protrusion is vertically overlapped with the second separation insulating layer.

11. A semiconductor device, comprising:
a selection line extending in a first direction;
first and second vertically stacked memory cell strings arranged in a second direction crossing the first direction, the first and second vertically stacked memory cell strings commonly coupled to the same selection line;
first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;
a first sub-interconnection coupling the first vertically stacked memory cell string to the first bit line; and
a second sub-interconnection coupling the second vertically stacked memory cell string to the second bit line,
wherein the first sub-interconnection has a protrusion protruding in the first direction, and
wherein the second sub-interconnection has a substantially rectangular shape extending in the second direction in plan view.

12. The device of claim 11 , wherein the selection line, the sub-interconnections, and the bit lines are sequentially provided on a substrate,
the vertically stacked memory cell strings are connected to the substrate,
the bit lines are provided on the vertically stacked memory cell strings, and
the sub-interconnections are provided between the vertically stacked memory cell strings and the bit lines.

13. The device of claim 11 , wherein each of the sub-interconnections has a longitudinal axis and a short axis,
a central part of the first sub-interconnection protrudes in the first direction along the short axis, and
the second sub-interconnection extends along the second direction without a protrusion.

14. The device of claim 13 , wherein a length of the first sub-interconnection in the longitudinal axis is different from that of the second sub-interconnection.

15. The device of claim 11 , wherein the selection line comprises first, second and third selection lines extending in the first direction, the selection lines spaced apart from each other in the second direction, and
wherein the device further comprises third and fourth vertically stacked memory cell strings arranged in the second direction, wherein the third vertically stacked memory cell string is coupled to the first selection line, the first and second vertically stacked memory cell strings are commonly coupled to the second selection line, and the fourth vertically stacked memory cell string is coupled to the third selection line.

16. The device of claim 15 , wherein the first sub-interconnection connects the first and third vertically stacked memory cell strings to the first bit line, and
wherein the second sub-interconnection connects the third and fourth vertically stacked memory cell strings to the second bit line.

17. The device of claim 15 , wherein the first sub-interconnection is connected to the first bit line through the protrusion.

18. The device of claim 15 , further comprising:
a first separation insulating layer extending in the first direction, the first separation insulating layer provided between the first and second selection lines.

19. The device of claim 18 , wherein the protrusion is vertically overlapped with the first separation insulating layer.

20. The device of claim 19 , further comprising:
a second separation insulating layer extending in the first direction, the separation insulating layer provided between the second and third selection lines,
wherein the sub-interconnection is vertically overlapped with the second separation insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seol Kwang-Soo
• Cho Seong-Soon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title