Vertical type memory device

Patent metadata

Field	Value
Publication number	US-9466613-B2
Application number	US-201615144863-A
Country	US
Kind code	B2
Filing date	May 3, 2016
Priority date	Oct 5, 2012
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.

First claim

The invention claimed is:

1. A semiconductor device comprising:
first and second selection lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction;
first vertically-stacked memory cell strings coupled to the first selection line;
second vertically-stacked memory cell strings coupled to the second selection line;
a first sub-interconnection coupling one of the first vertically-stacked memory cell strings to one of the second vertically-stacked memory cell strings;
a second sub-interconnection that is adjacent first sub-interconnection in the first direction; and
bit lines extending in the second direction and coupled to respective ones of the first and second sub-interconnections,
wherein the first sub-interconnection and the second sub-interconnection comprise respective first and second protrusions that protrude in the first direction, and
wherein a length of the first sub-interconnection in the second direction is different from a length of the second sub-interconnection in the second direction.

2. The device of claim 1 ,
wherein the first sub-interconnection comprises one among a plurality of first sub-interconnections and the second sub-interconnection comprises one among a plurality of second sub-interconnections, and
wherein the plurality of first sub-interconnections and the plurality of second sub-interconnections are alternatingly arranged in the first direction.

3. The device of claim 1 , further comprising a substrate,
wherein the first and second selection lines, the first and second sub-interconnections, and the bit lines are sequentially arranged on the substrate,
wherein the bit lines are on the first and second vertically-stacked memory cell strings, and
wherein the first and second sub-interconnections are between the first and second vertically-stacked memory cell strings and the bit lines.

4. The device of claim 1 ,
wherein each of the first and second sub-interconnections has a longitudinal axis and a short axis,
wherein a central portion of the first sub-interconnection protrudes in the first direction along the short axis, and
wherein a central portion of the second sub-interconnection protrudes in the first direction along the short axis.

5. The device of claim 4 , wherein the first sub-interconnection comprises a shorter length, relative to the second sub-interconnection, along the longitudinal axis.

6. The device of claim 1 , wherein the first and the second sub-interconnections are connected to the bit lines through the respective first and second protrusions.

7. The device of claim 1 , further comprising:
a separation insulating layer between the first and second selection lines and extending in the first direction,
wherein at least one of the first and second protrusions vertically overlaps the separation insulating layer.

8. The device of claim 1 , further comprising:
a third selection line extending in the first direction;
third vertically-stacked memory cell strings coupled to the third selection line; and
a third sub-interconnection coupling one of the third vertically-stacked memory cell strings to one of the second vertically-stacked memory cell strings.

9. The device of claim 8 ,
wherein the third sub-interconnection comprises a third protrusion protruding in a direction opposite to the first direction.

10. The device of claim 9 , further comprising:
a first separation insulating layer between the first and second selection lines and extending in the first direction; and
a second separation insulating layer between the second and third selection lines and extending in the first direction,
wherein the first and second protrusions vertically overlap the first separation insulating layer, and
wherein the third protrusion vertically overlaps the second separation insulating layer.

Assignees

• Seol Kwang-Soo
• Cho Seong-Soon
• Samsung Electronics Co Ltd

Inventors

• Seol Kwang-Soo
• Cho Seong-Soon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title