Vertical type memory device

Patent metadata

Field	Value
Publication number	US-9287167-B2
Application number	US-201414200002-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Oct 5, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.

First claim

The invention claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a plurality of memory cell strings on a substrate;
coupling a single-body interconnection to at least two of the memory cell strings; and
coupling a bitline to the single-body interconnection,
wherein coupling the single-body interconnection to the at least two of the memory cell strings comprises forming the single-body interconnection including a body extending along a first direction and a protrusion protruding from the body along a second direction,
wherein the first and second directions are substantially parallel to the substrate, and
wherein the single-body interconnection has one end part coupled to one memory cell string and another end part coupled to another memory cell string.

2. The method of claim 1 , wherein forming the single-body interconnection comprises forming a mask pattern including a pair of first sub-mask patterns corresponding to the body and a second sub-mask pattern corresponding the protrusion.

3. The method of claim 2 , wherein the first sub-mask patterns are spaced apart from each other along the first direction and the second sub-mask pattern is disposed between the first sub masks.

4. The method of claim 3 , wherein the second sub-mask pattern is shifted from the first sub-mask patterns along the second direction by a first distance.

5. The method of claim 4 , wherein the mask further includes a pair of third sub-mask patterns between the first sub-mask patterns and the second sub-mask pattern.

6. The method of claim 5 , wherein the third sub-mask patterns are shifted from the first sub-mask patterns along the second direction by about half of the first distance.

7. The method of claim 5 , wherein the third sub-mask patterns are in a plural.

8. The method of claim 3 , wherein the mask pattern has a staircase shape.

9. The method of claim 2 , wherein coupling the bitline to the single-body interconnection comprises forming the bitline extending along the first direction and shifted from the single-body interconnection along the second direction.

10. The method of claim 1 , forming the plurality of memory cell strings comprising:
forming gate structures on a semiconductor substrate, each of the gate structures including insulating patterns and gate electrodes spaced apart from each other with the insulating patterns interposed therebetween;
forming vertical pillars extending through each of the gate structures to be connected to the semiconductor substrate; and
forming a separation insulating layer in separation regions between the gate structures.

11. The method of claim 10 , wherein the second sub-mask pattern is provided vertically over the separation insulating layer.

12. The method of claim 11 , wherein each of the first sub-mask patterns is provided vertically over each of the vertical pillars.

13. The method of claim 10 , forming the gate structures comprising:
forming a buffer dielectric layer over the semiconductor substrate;
repeatedly forming a stack of a sacrificial layer and an insulating layer over the buffer dielectric layer;
forming the vertical pillars extending through the stack of sacrificial layer and the insulating layer to be connected to the semiconductor substrate;
forming the separation regions by patterning the buffer dielectric layer, the sacrificial layer, and the insulating layers to expose a portion of the semiconductor substrate;
removing the patterned sacrificial layers to form recessed regions that expose portions of sidewalls of the vertical pillars;
forming information storage elements in the recessed regions; and
forming a conductive layer on the information storage elements in the recessed regions.

14. A method of fabricating a semiconductor device, comprising:
forming a plurality of vertically stacked memory cell strings;
forming a single-body interconnection to couple at least two of the plurality of vertically stacked memory cell strings; and
coupling a bitline to the interconnection,
wherein coupling the single-body interconnection to the at least two of the memory cell strings comprises forming the single-body interconnection including a body extending along a first direction and a protrusion protruding from the body along a second direction,
wherein the first and second directions are substantially perpendicular to a direction in which the memory cell strings are stacked, and
wherein the single-body interconnection has one end part coupled to one memory cell string and another end part coupled to another memory cell string.

15. The method of claim 14 , wherein the coupling of the bit line to the single-body interconnection is performed after forming the single-body interconnection.

16. The method of claim 14 , wherein the single-body interconnection has a longitudinal axis and a short axis, wherein a central part of the single-body interconnection protrudes in a first direction along the short axis and wherein the bit line extends in a second direction along the longitudinal axis.

17. The method of claim 14 , wherein the single-body interconnection has a first portion having a first longitudinal center axis and a second portion, arranged at a central portion of the single-body interconnection, said second portion having a second longitudinal center axis, said second longitudinal center axis being parallel to and offset from the first axis.

18. The method of claim 14 , wherein the coupling of the bitline to the single-body interconnection comprises directly coupling the bitline with the single-body interconnection.

19. The method of claim 14 , wherein the first direction is substantially perpendicular to the second direction.

20. The method of claim 1 , wherein the single-body interconnection is coupled to the bit line through the protrusion.

Assignees

• Seol Kwang Soo
• Cho Seong Soon
• Go Byungjoo
• Kim Hongsoo
• Samsung Electronics Co Ltd

Inventors

• Seol Kwang Soo
• Cho Seong Soon
• Go Byungjoo
• Kim Hongsoo

Classifications

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D30/6893 Primary

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title