Vertical type memory device

Patent metadata

Field	Value
Publication number	US-9257572-B2
Application number	US-201313844337-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Oct 5, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a single selection line extending in a first direction;
first and second vertically stacked memory cell strings arranged in a second direction crossing the first direction, the first and second vertically stacked memory cell strings commonly coupled to the single selection line;
first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;
a first sub-interconnection coupling the first vertically stacked memory cell string to the first bit line; and
a second sub-interconnection coupling the second vertically stacked memory cell string to the second bit line,
wherein the vertically stacked memory cell strings are respectively coupled to different bit lines.

2. The device of claim 1 , wherein the single selection line, the sub-interconnections, and the bit lines are sequentially provided on a substrate,
wherein the vertically stacked memory cell strings are connected to the substrate,
wherein the bit lines are provided on the vertically stacked memory cell strings, and
wherein the sub-interconnections are provided between the vertically stacked memory cell strings and the bit lines.

3. The device of claim 1 , wherein each of the sub-interconnections has a longitudinal axis and a short axis,
a central part of each of the sub-interconnections protrudes in the first direction along the short axis, and
the longitudinal axis extends in the second direction.

4. A semiconductor device, comprising:
first and second selection lines extending in a first direction, the first and second selection lines spaced apart from each other in a second direction crossing the first direction;
first and second vertically stacked memory cell strings arranged in the second direction, the first vertically stacked memory cell string being coupled to the first selection line, the second vertically stacked memory cell string being coupled to the second selection line;
a bit line extending in the second direction; and
a single-body sub-interconnection extending in the second direction coupling the first and second vertically stacked memory cell strings to the bit line wherein the single body sub-interconnection has one end part coupled to the first vertically stacked memory cell string and another end part coupled to the second vertically stacked memory cell string.

5. The device of claim 4 , wherein the sub-interconnection has a longitudinal axis and a short axis,
wherein a central part of the single body sub-interconnection protrudes in the first direction along the short axis, and
wherein the longitudinal axis extends in the second direction.

6. The device of claim 5 , further comprising a separation insulating layer extending in the first direction, the separation insulating layer provided between the first and second selection lines.

7. The device of claim 6 , wherein the central part of the single body sub-interconnection is vertically overlapped with the separation insulating layer.

8. The device of claim 6 , wherein the single body sub-interconnection is connected to the first bit line through the central part of the single body sub-interconnection.

9. The device of claim 5 , further comprising:
first contacts connecting the vertically stacked memory cell strings to the single body sub-interconnection; and
a second contact connecting the single body sub-interconnection to the first bit line.

10. The device of claim 9 , wherein the second contact is shifted from the first contacts along the first direction.

11. A semiconductor device, comprising:
first, second and third selection lines extending in a first direction, the selection lines spaced apart from each other in a second direction crossing the first direction;
first, second, third and fourth vertical pillars arranged in the second direction, the first vertical pillar being coupled to the first selection line, the second and third vertical pillars being commonly coupled to the second selection line, and the fourth vertical pillar being coupled to the third selection line;
first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;
a first sub-interconnection coupling the first and second vertical pillars to the first bit line; and
a second sub-interconnection coupling the third and fourth vertical pillars to the second bit line.

12. The device of claim 11 , wherein each of the sub-interconnections has a longitudinal axis and a short axis,
the first sub-interconnection having a first protrusion protruding in the first direction along the short axis,
the second sub-interconnection having a second protrusion protruding in an opposite direction to the first direction along the short axis, and
the longitudinal axis extending in the second direction.

13. The device of claim 12 , wherein the first sub-interconnection is connected to the first bit line through the first protrusion, and wherein the second sub-interconnection is connected to the second bit line through the second protrusion.

14. The device of claim 12 , wherein the selection lines, the sub-interconnections and the bit lines are sequentially provided on a substrate,
the device further comprising:
a first separation insulating layer extending in the first direction, the first separation insulating layer provided between the first and second selection lines.

15. The device of claim 14 , wherein the first protrusion is vertically overlapped with the first separation insulating layer.

16. The device of claim 15 , further comprising:
cell gates between the substrate and the selection lines, and
wherein the vertical pillars penetrate the cell gates and are electrically connected to the substrate.

17. The device of claim 16 , further comprising:
a second separation insulating layer extending in the first direction, the second separation insulating layer provided between the second and third selection lines, and
wherein the first separation insulating layer contacts with the substrate, and the second separation layer provided above the cell gates.

18. The device of claim 17 , wherein the first protrusion is vertically overlapped with the first separation insulating layer, and the second protrusion is vertically overlapped with the second separation insulating layer.

19. The device of claim 16 , further comprising:
an information storage element between the cell gates and the vertical pillars.

20. The device of claim 16 , wherein the first sub-interconnection has a shorter length along the longitudinal axis than that of the second sub-interconnection.

Assignees

• Seol Kwang-Soo
• Cho Seong-Soon
• Samsung Electronics Co Ltd

Inventors

• Seol Kwang-Soo
• Cho Seong-Soon

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title