Method and structure for a logic device and another device
US-12557353-B2 · Feb 17, 2026 · US
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Arnold John Christopher patents
Arnold John Christopher is listed as an inventor on 44 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Arnold John Christopher |
| Total patents | 44 |
| First publication | Apr 5, 2018 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Diffusion break between passive device and logic device with backside contact
US-12550351-B2 · Feb 10, 2026 · US
Two-dimensional self-aligned backside via-to-backside power rail (VBPR)
US-12527068-B2 · Jan 13, 2026 · US
Self-aligned via connection with enlarged contact area to subtractive line
US-2025391756-A1 · Dec 25, 2025 · US
Dielectric liner protection to prevent shorting to gate
US-2025386559-A1 · Dec 18, 2025 · US
Semiconductor passive device integration for silicon-on-insulator substrate
US-12489035-B2 · Dec 2, 2025 · US
Semiconductor backside contact spacer engineering
US-2025261424-A1 · Aug 14, 2025 · US
Interconnect with topvia
US-2025226319-A1 · Jul 10, 2025 · US
Stacked transistor backside contact formation
US-2025185331-A1 · Jun 5, 2025 · US
Dual liners for aggressive nanosheet spacing with backside contacts
US-2025169160-A1 · May 22, 2025 · US
Recent patents
Latest publications not already listed above.
Stacked fet power delivery network formation
US-2025157928-A1 · May 15, 2025 · US
Module-less nanosheet fets with direct backside contact
US-2025151345-A1 · May 8, 2025 · US
Self-aligned topvia and metal line with increased height
US-2025125193-A1 · Apr 17, 2025 · US
Embedded metal contamination removal from BEOL wafers
US-12272545-B2 · Apr 8, 2025 · US
Backside power rails and power distribution network for density scaling
US-12268031-B2 · Apr 1, 2025 · US
Stacked field effect transistors
US-2025048688-A1 · Feb 6, 2025 · US
Diffusion break between passive device and logic device with backside contact
US-2025046714-A1 · Feb 6, 2025 · US
Extended backside contact in stack nanosheet
US-2025031430-A1 · Jan 23, 2025 · US
Semiconductor passive device integration for silicon-on-insulator substrate
US-2024395664-A1 · Nov 28, 2024 · US
Electrostatic discharge using backside power distribution network
US-2024363617-A1 · Oct 31, 2024 · US
Flexible self-aligned power via shape with gate cut first
US-2024321957-A1 · Sep 26, 2024 · US
Subtractive metal via with metal bridge
US-2024282704-A1 · Aug 22, 2024 · US
Subtractive patterning of interconnect structures
US-12020949-B2 · Jun 25, 2024 · US
Method and structure for a logic device and another device
US-2023378258-A1 · Nov 23, 2023 · US
Two-dimensional self-aligned backside via-to-backside power rail (vbpr)
US-2023215767-A1 · Jul 6, 2023 · US
Backside power rails and power distribution network for density scaling
US-2023207553-A1 · Jun 29, 2023 · US
Spin on scaffold film for forming topvia
US-11688636-B2 · Jun 27, 2023 · US
Subtractive patterning of interconnect structures
US-2023084739-A1 · Mar 16, 2023 · US
Spin on scaffold film for forming topvia
US-2022406657-A1 · Dec 22, 2022 · US
Selective gas etching for self-aligned pattern transfer
US-11302533-B2 · Apr 12, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 42 |
| Tessera Inc | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/6757 | 18 |
| H10D64/017 | 17 |
| H10D30/6735 | 17 |
| H10D30/43 | 16 |
| H10D62/121 | 16 |