Integrated circuit devices having through silicon via structures and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9379042-B2
Application number	US-201414504647-A
Country	US
Kind code	B2
Filing date	Oct 2, 2014
Priority date	Oct 15, 2013
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a capacitor comprising an electrode on a substrate;
a through-silicon-via (TSV) landing pad on the substrate, the TSV landing pad comprising the same material as the electrode;
a multi-layered interconnection structure on the TSV landing pad; and
a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad,
wherein the electrode and the TSV landing pad each comprise a first non-metallic conductive layer and a second conductive layer that includes at least one metal,
wherein the first conductive layer is closer to the substrate compared to the second conductive layer.

2. The integrated circuit device of claim 1 , wherein the capacitor comprises a lower electrode connected to an active region of the substrate, an upper electrode on the lower electrode, and a dielectric film interposed between the lower electrode and the upper electrode,
wherein the TSV landing pad comprises the same material as the upper electrode.

3. The integrated circuit device of claim 1 , further comprising a bit line between the substrate and the capacitor on the substrate,
wherein a thickness of the TSV landing pad is larger than a thickness of the bit line.

4. The integrated circuit device of claim 1 , wherein the first conductive layer is interposed between the substrate and the second conductive layer.

5. The integrated circuit device of claim 1 , wherein the TSV structure has an upper surface having a first portion that directly contacts the TSV landing pad and a second portion that is spaced apart from the TSV landing pad.

6. The integrated circuit device of claim 1 , wherein at least a portion of the TSV landing pad comprises a mesh pattern.

7. The integrated circuit device of claim 1 , wherein at least a portion of the TSV landing pad comprises a plurality of spaced apart patterns.

8. The integrated circuit device of claim 2 , further comprising a contact plug connected between an interconnection line of the multi-layered interconnection structure and the TSV landing pad, and wherein a portion of the upper electrode in a memory cell area of the integrated circuit device has a thickness that is substantially equal to a thickness of the landing pad.

9. The integrated circuit device of claim 1 , further comprising a TSV area dielectric film on a surface of the TSV landing pad that faces the substrate,
wherein the TSV area dielectric film comprises the same material as a dielectric film of the capacitor.

10. An integrated circuit device comprising:
a substrate comprising first and second areas having different pattern formation densities;
a first insulating layer on the first area of the substrate;
a second insulating layer on the second area of the substrate;
a capacitor on the first insulating layer;
a through-silicon-via (TSV) landing pad on the second insulating layer, the TSV landing pad comprising the same material as an electrode of the capacitor;
a multi-layered interconnection structure on the TSV landing pad; and
a TSV structure passing through the substrate and the second insulating layer, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad; and
a TSV area dielectric film on a surface of the TSV landing pad that faces the substrate,
wherein the TSV area dielectric film comprises the same material as a dielectric film of the capacitor.

11. The integrated circuit device of claim 10 , wherein the first area is a memory cell array area, and the second area is a TSV area that is spaced apart from the memory cell array area.

12. An integrated circuit device, comprising:
a substrate having a device region and a through-silicon-via (TSV) region;
a plurality of capacitors on the substrate in the device region, the capacitors having first electrodes, and a common second electrode;
a TSV landing pad on the substrate in the TSV region, the TSV landing pad formed of the same material as the common second electrode;
a first contact plug on the common second electrode opposite the substrate;
a second contact plug on the TSV landing pad opposite the substrate; and
a TSV structure passing through the substrate to connect to the TSV landing pad.

13. The integrated circuit device of claim 12 , wherein the common second electrode is a multi-layer electrode that includes a first non-metallic layer and a second metal-containing layer that is on the first non-metallic layer opposite the substrate.

14. The integrated circuit device of claim 13 , wherein the first non-metallic layer comprises a SiGe layer and wherein a portion of the second electrode in the device region has a thickness that is substantially equal to a thickness of the TSV landing pad.

15. The integrated circuit device of claim 13 , wherein one of the first non-metallic layer and the second metal-containing layer is a continuous layer and the other of the first non-metallic layer and the second metal-containing layer is a discontinuous layer.

16. The integrated circuit device of claim 12 , wherein a central portion of a first side of the TSV landing pad that is closest to the substrate is recessed.

17. The integrated circuit device of claim 10 , wherein the TSV landing pad comprises a multi-layer landing pad in which at least two conductive layers that are formed of different materials are stacked.

18. The integrated circuit device of claim 12 , further comprising a TSV area dielectric film on a surface of the TSV landing pad that faces the substrate,
wherein the TSV area dielectric film comprises the same material as a dielectric film of a first of the plurality of capacitors.

19. The integrated circuit device of claim 12 , further comprising a bit line between the substrate and a first of the plurality of capacitors,
wherein a thickness of the TSV landing pad is larger than a thickness of the bit line.

Assignees

• Park Jae-Hwa
• Bang Suk-Chul
• Park Byung-Lyul
• Moon Kwang-Jin
• Samsung Electronics Co Ltd

Inventors

• Park Jae-Hwa
• Bang Suk-Chul
• Park Byung-Lyul
• Moon Kwang-Jin

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title