Hybrid power rail structure

Patent metadata

Field	Value
Publication number	US-2020105671-A1
Application number	US-201916559547-A
Country	US
Kind code	A1
Filing date	Sep 3, 2019
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.

First claim

What is claimed is:

1 . An integrated circuit structure comprising:
a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side; a first power rail extending in a first direction, being embedded in the front side of the substrate and configured to provide a first supply voltage; a second power rail configured to provide a second supply voltage different from the first supply voltage, the second power rail extending in the first direction, being embedded in the front side of the substrate and being separated from the first power rail in a second direction different from the first direction; a first device positioned between the first power rail and the second power rail, and located on the front side of the substrate; and a first via structure extending to the back side of the substrate and being electrically coupled to the second power rail.

2 . The integrated circuit of claim 1 , wherein the first power rail comprises a metal layer positioned on the first device.

3 . The integrated circuit of claim 1 , wherein the second power rail is a buried power rail.

4 . The integrated circuit of claim 1 , wherein the first power rail is electrically coupled to a conductive device.

5 . The integrated circuit of claim 4 , wherein the conductive device extends in at least the first direction or the second direction, being above the first device, the first power rail and the second power rail.

6 . The integrated circuit of claim 4 , wherein the first power rail uses a second via structure to be electrically coupled to the conductive device.

7 . The integrated circuit of claim 1 , wherein the first supply voltage and the second supply voltage are of different values.

8 . The integrated circuit of claim 1 , wherein the first via structure is a through silicon via.

9 . The integrated circuit of claim 1 , wherein the first device comprises passive devices and active devices.

10 . A method of forming an integrated circuit (IC), the method comprising:
generating, by a processor, a cell layout design of the integrated circuit, wherein the generating of the cell layout design comprises: generating a first power rail layout pattern extending in a first direction and corresponding to a first power rail in a front side of a substrate and configured to provide a first supply voltage; generating a second power rail layout pattern extending in the first direction and separated from the first power rail layout pattern in a second direction different from the first direction, the second power rail layout pattern corresponding to a second power rail in the front side of the substrate and configured to provide a second supply voltage different from the first supply voltage; generating a set of first device layout patterns positioned between the first power rail layout pattern and the second power rail layout pattern and corresponding to a set of devices; generating a first via layout pattern corresponding to a first via structure extending to a backside of the substrate and electrically coupled to the second power rail; and manufacturing the integrated circuit based on the cell layout design.

11 . The method of claim 10 , wherein the generating the first power rail layout pattern comprises positioning a metal layer on the set of first device layout patterns to define the first power rail layout pattern.

12 . The method of claim 10 , wherein the generating the second power rail layout pattern comprises generating a buried power rail layout pattern to define the second power rail layout pattern.

13 . The method of claim 10 further comprising generating a conductive structure layout corresponding to fabricating a conductive structure electrically coupled to the first power rail.

14 . The method of claim 13 , wherein the generating the conductive structure layout comprises extending in at least the first direction or the second direction, being above the set of devices, the first power rail and the second power rail.

15 . The method of claim 10 , wherein the generating the first via layout pattern comprises generating a through silicon via layout pattern corresponding to fabricating a through silicon via.

16 . The method of claim 10 , wherein generating the set of first device layout patterns comprises generating passive device layout patterns and active device layout patterns.

17 . An integrated circuit comprising:
a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side; a hybrid power rail structure at least partially embedded in the front side of the substrate comprising:
a first buried power rail configured to provide a first supply voltage;
a second buried power rail coupled to the first buried power rail and configured to provide a second supply voltage; and
a via structure electrically coupled to the second buried power rail and configured to provide backside power.

18 . The integrated circuit of claim 17 , wherein
the first buried power rail has a first height along a direction between the front side and the back side, the second buried power rail has a second height along the direction, and the first height and the second height are distinct from each other.

19 . The integrated circuit of claim 17 , wherein the first buried power rail comprises a bottom protective layer.

20 . The integrated circuit of claim 17 , wherein the via structure is a through silicon via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Wei-An
• Tzeng Jiann-Tyng
• Lin Wei-Cheng

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G03F1/36

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title