Semiconductor devices including shallow trench isolation (sti) liners

Patent metadata

Field	Value
Publication number	US-2016276342-A1
Application number	US-201614988039-A
Country	US
Kind code	A1
Filing date	Jan 5, 2016
Priority date	Mar 18, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

Semiconductor devices including STI liners are provided. The semiconductor devices may include a STI trench that defines an active region in a substrate, a STI liner that extends conformally along side walls and a bottom surface of the STI trench, a device isolation film that is on the STI liner and fills up at least a part of the STI trench, a first gate structure that is disposed on the active region, and a second gate structure that is spaced apart from the first gate structure. The second gate structure may include a gate insulating film contacting the device isolation film, a gate electrode on the gate insulating film, and spacers on both sides of the gate electrode. Lower surfaces of the spacers may contact an upper surface of the STI liner.

First claim

1 . A semiconductor device comprising:
an active region on a substrate, the active region being defined by a shallow trench isolation (STI) trench; a STI liner conformally disposed on side walls and a bottom surface of the STI trench; a device isolation film on the STI liner, the device isolation film filling at least a part of the STI trench; a first gate structure on the active region; and a second gate structure spaced apart from the first gate structure, wherein the second gate structure includes a gate insulating film being in contact with the device isolation film, a gate electrode on the gate insulating film, and spacers on both sides of the gate electrode, and wherein lower surfaces of the spacers contact an upper surface of the STI liner.

2 . The semiconductor device of claim 1 , further comprising:
a source or a drain on at least one side of the first gate structure, wherein the source or the drain contacts an outer surface of the STI liner.

3 . The semiconductor device of claim 2 , wherein a part of the source or the drain has an upper surface higher than an upper surface of the device isolation film.

4 . The semiconductor device of claim 3 , wherein a part of the source or the drain contacts a part of a lower surface of the first gate structure or overlaps the first gate structure.

5 . The semiconductor device of claim 2 , wherein the source or the drain is formed by an epitaxial growth method.

6 . The semiconductor device of claim 1 , wherein the spacers include a first spacer part on one side of the gate electrode and a second spacer part on the other side of the gate electrode, and
wherein the first spacer part contacts a first upper surface of the STI liner, and the second spacer part contacts a second upper surface of the STI liner that is spaced apart from the first upper surface of the STI liner.

7 . The semiconductor device of claim 1 , wherein the gate insulating film is conformally disposed along side walls of the spacers and an upper surface of the device isolation film, and
wherein the gate electrode includes a metal layer conformally disposed on an upper surface of the gate insulating film.

8 . The semiconductor device of claim 1 , wherein an upper surface of the device isolation film and an upper surface of the substrate are coplanar.

9 . The semiconductor device of claim 1 , wherein the lower surfaces of the spacers contact only an upper surface of the device isolation film.

10 . The semiconductor device of claim 1 , further comprising:
a third gate structure spaced apart from the second gate structure, wherein a lower surface of the third gate structure is disposed on the device isolation film.

11 . The semiconductor device of claim 1 , wherein the STI liner has a double-layer structure including a silicon oxide (SiO 2 ) layer and a silicon nitride (SiN) layer.

12 . A semiconductor device comprising:
a plurality of fins extending in a first direction on a substrate; a first gate structure and a second gate structure extending in a second direction and being spaced apart from each other, the second direction crossing the first direction; a shallow trench isolation (STI) trench between the plurality of fins; a STI liner conformally disposed along a part of side walls and a bottom surface of the STI trench; and a device isolation film on the STI liner and filling at least a part of the STI trench, wherein the second gate structure includes a gate insulating film, a gate electrode, and spacers on both sides of the gate electrode, wherein the spacers of the second gate structure include a first spacer part on one side of the gate electrode of the second gate structure and a second spacer part on the other side of the gate electrode of the second gate structure, and wherein the first spacer part contacts an upper surface of at least one of the plurality of fins, and the second spacer part contacts an upper surface of the device isolation film.

13 . The semiconductor device of claim 12 , wherein the gate insulating film is conformally disposed along side walls of the spacers, the upper surface of the device isolation film, or upper surfaces of the plurality of fins, and
wherein the gate electrode includes a metal layer conformally disposed along an upper surface of the gate insulating film.

14 . A semiconductor device comprising:
a substrate including a first region and a second region; a plurality of fins extending in a first direction on the first region or the second region; a shallow trench isolation (STI) trench between the plurality of fins; a gate structure crossing the plurality of fins and extending in a second direction different from the first direction; a deep trench isolation (DTI) trench between the first region and the second region; a DTI liner conformally disposed along side walls and a bottom surface of the DTI trench; and a device isolation film on the DTI liner and filling at least a part of the DTI trench, wherein a lower surface of the STI trench is higher than a lower surface of the DTI trench.

15 . The semiconductor device of claim 14 , wherein an upper surface of the DTI liner and the lower surface of the STI trench are coplanar.

16 . The semiconductor device of claim 14 , further comprising:
a STI liner conformally disposed along side walls and a bottom surface of the STI trench, wherein the device isolation film is disposed on the STI liner and fills at least a part of the STI trench.

17 . The semiconductor device of claim 16 , wherein an upper surface of the DTI liner is higher than the lower surface of the STI trench.

18 . The semiconductor device of claim 16 , wherein the STI liner and the DTI liner have a double film structure including a silicon oxide (SiO 2 ) layer and a silicon nitride (SiN) layer.

19 . The semiconductor device of claim 14 , wherein the gate structure includes a gate insulating film which is in contact with the device isolation film and the plurality of fins, a gate electrode on the gate insulating film, and spacers on both sides of the gate electrode,
wherein the gate insulating film is conformally disposed along side walls of the spacers, an upper surface of the device isolation film, or upper surfaces of the plurality of fins, and wherein the gate electrode includes a metal layer conformally disposed along an upper surface of the gate insulating film.

20 . The semiconductor device of claim 19 , wherein the gate structure includes a first gate structure and a second gate structure,
wherein the first gate structure overlaps the plurality of fins, and wherein the second gate structure overlaps the device isolation film and does not overlap the plurality of fins.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Sun-Me
• Lim Young-Dal
• Cho Hag-Ju

Classifications

• H10D30/795 Primary

  being in lateral device isolation regions, e.g. STI · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/853

  comprising FinFETs · CPC title