Semiconductor device with a protective diode connected to a fuse
US-12571837-B2 · Mar 10, 2026 · US
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Hook Terence patents
Hook Terence is listed as an inventor on 43 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hook Terence |
| Total patents | 43 |
| First publication | Jul 5, 2018 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Method and structure for a logic device and another device
US-12557353-B2 · Feb 17, 2026 · US
FVBP without backside Si recess
US-12557320-B2 · Feb 17, 2026 · US
Protection diode to prevent charge damage during MOL
US-12550448-B2 · Feb 10, 2026 · US
Stacked FET vertical diode
US-12527076-B2 · Jan 13, 2026 · US
Semiconductor device with a protective diode connected to a fuse
US-2025298073-A1 · Sep 25, 2025 · US
High aspect ratio contact structure with multiple metal stacks
US-12268026-B2 · Apr 1, 2025 · US
Size-efficient mitigation of latchup and latchup propagation
US-12230629-B2 · Feb 18, 2025 · US
Double-sided integrated circuit with damage sensor
US-2025006629-A1 · Jan 2, 2025 · US
Three dimensional mechanically bolting staple fill
US-2025006664-A1 · Jan 2, 2025 · US
Recent patents
Latest publications not already listed above.
Double-sided integrated circuit with electrostatic guard ring
US-2025006663-A1 · Jan 2, 2025 · US
Stacked nanosheet fets with gate dielectric fill
US-2025006736-A1 · Jan 2, 2025 · US
Double-sided integrated circuit with stabilizing cage
US-2025006590-A1 · Jan 2, 2025 · US
Monolith structure for bspdn semiconductor devices
US-2024429178-A1 · Dec 26, 2024 · US
Semiconductor device design mitigating latch-up
US-12176289-B2 · Dec 24, 2024 · US
PASSIVE DEVICE WITH THINNER Si LAYER
US-2024413164-A1 · Dec 12, 2024 · US
FVBP WITHOUT BACKSIDE Si RECESS
US-2024405112-A1 · Dec 5, 2024 · US
Stacked fet vertical diode
US-2024379658-A1 · Nov 14, 2024 · US
Stacked devices containing at least one lateral diode
US-2024379657-A1 · Nov 14, 2024 · US
Electrostatic discharge using backside power distribution network
US-2024363617-A1 · Oct 31, 2024 · US
Heat pipe for vertically stacked field effect transistors
US-12040250-B2 · Jul 16, 2024 · US
Heat dissipation structures for bonded wafers
US-2024203816-A1 · Jun 20, 2024 · US
Gate-all-around field effect transistor having multiple threshold voltages
US-12015069-B2 · Jun 18, 2024 · US
Protection diode to prevent charge damage during mol
US-2024096871-A1 · Mar 21, 2024 · US
Structure having enhanced gate resistance
US-2024096948-A1 · Mar 21, 2024 · US
Heat pipe for vertically stacked field effect transistors
US-2023411241-A1 · Dec 21, 2023 · US
Method and structure for a logic device and another device
US-2023378258-A1 · Nov 23, 2023 · US
High aspect ratio contact structure with multiple metal stacks
US-2023317802-A1 · Oct 5, 2023 · US
Size-efficient mitigation of latchup and latchup propagation
US-2023317722-A1 · Oct 5, 2023 · US
Semiconductor device design mitigating latch-up
US-2023307363-A1 · Sep 28, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 39 |
| Globalfoundries Us Inc | 3 |
| Globalfoundries Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/6735 | 19 |
| H10D62/121 | 18 |
| H10D30/43 | 18 |
| H10D64/017 | 16 |
| H10D30/014 | 15 |