Strain Enhancement for FinFETs

Patent metadata

Field	Value
Publication number	US-2016336237-A1
Application number	US-201615220989-A
Country	US
Kind code	A1
Filing date	Jul 27, 2016
Priority date	Jan 13, 2014
Publication date	Nov 17, 2016
Grant date	—

Abstract

An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

First claim

What is claimed is:

1 . A method comprising:
etching a semiconductor substrate to form a first trench in a first device region and a second trench in a second device region, wherein remaining portions of the semiconductor substrate comprise:
a first semiconductor strip with a first sidewall exposed to the first trench; and
a second semiconductor strip with a second sidewall exposed to the second trench;
forming a first dielectric liner extending on the first sidewall of the first semiconductor strip and the second sidewall of the second semiconductor strip; removing the first dielectric liner from the second trench, wherein the first dielectric liner is left in the first device region; forming a first isolation region over the first dielectric liner and in the first trench, wherein a sidewall and a bottom surface of the first isolation region is in contact with a sidewall and a top surface of the first dielectric liner; and forming a second isolation region in the second trench, wherein the first isolation region and the second isolation region are formed simultaneously.

2 . The method of claim 1 , wherein the second isolation region is in physical contact with the second sidewall of the second semiconductor strip.

3 . The method of claim 1 further comprising, before the forming the first isolation region and the forming the second isolation region:
forming a second dielectric liner extending on the second sidewall of the second semiconductor strip, wherein the second dielectric liner extends into the first device region; and
removing the second dielectric liner from the first device region.

4 . The method of claim 3 , wherein the first dielectric liner and the second dielectric liner comprise different materials.

5 . The method of claim 1 , wherein the second isolation region is in physical contact with a top surface of the semiconductor substrate, and the top surface of the semiconductor substrate is directly underlying the second trench.

6 . The method of claim 1 further comprising, before forming the first dielectric liner, filling bottom portions of the first trench and the second trench with additional isolation regions, wherein top portions of the first trench and the second trench are not filled with the additional isolation regions.

7 . The method of claim 1 further comprising, before the forming the first isolation region, performing a treatment on the first dielectric liner.

8 . The method of claim 1 further comprising:
recessing the first isolation region and the first dielectric liner to form a recess; and
forming a gate dielectric on a top surface and a sidewall of the first semiconductor strip; and
forming a gate electrode over the gate dielectric.

9 . The method of claim 8 , wherein the first isolation region is recessed more than the first dielectric liner, and the gate dielectric contacts a sidewall of the first dielectric liner.

10 . A method comprising:
etching a semiconductor substrate to form a first trench and a second trench, wherein a remaining first portion of the semiconductor substrate forms a first semiconductor strip having a first sidewall exposed to the first trench, and a remaining second portion of the semiconductor substrate forms a second semiconductor strip having a second sidewall exposed to the second trench; forming a first dielectric liner, wherein the first dielectric liner extends into the first trench and the second trench to contact the first sidewall of the first semiconductor strip and the second sidewall of the second semiconductor strip, respectively; removing the first dielectric liner from the second trench, wherein the first dielectric liner is left in the first trench; forming a second dielectric liner extending into the first trench and the second trench, wherein the second dielectric liner is in contact with the second sidewall of the second semiconductor strip; removing the second dielectric liner from the first trench, wherein the second dielectric liner is left in the second trench; and simultaneously forming a first isolation region over the first dielectric liner and in the first trench and a second isolation region over the second dielectric liner and in the second trench.

11 . The method of claim 10 , wherein the first dielectric liner and the second dielectric liner apply different types of stresses to the first semiconductor strip and the second semiconductor strip, respectively.

12 . The method of claim 10 , wherein the first dielectric liner and the second dielectric liner are deposited as comprising different materials.

13 . The method of claim 10 , wherein both the first dielectric liner and the second dielectric liner are deposited as extending into a third trench, wherein the first dielectric liner is removed from a first portion of the third trench, and the second dielectric liner is removed from a second portion of the third trench.

14 . The method of claim 10 further comprising, before forming the first dielectric liner, filling bottom portions of the first trench and the second trench with additional isolation regions, wherein the first dielectric liner and the second dielectric liner are formed over the additional isolation regions.

15 . The method of claim 10 further comprising, before the forming the first isolation region, performing a treatment on the first dielectric liner.

16 . The method of claim 10 further comprising:
recessing the first isolation region and the first dielectric liner;
forming a first gate dielectric on a top surface and a sidewall of the first semiconductor strip; and
forming a first gate electrode over the first gate dielectric, wherein the first gate dielectric and the first gate electrode form portions of a first Fin Field-Effect Transistor (FinFET).

17 . The method of claim 16 further comprising:
recessing the second isolation region and the second dielectric liner;
forming a second gate dielectric on a top surface and a sidewall of the second semiconductor strip; and
forming a second gate electrode over the second gate dielectric, wherein the second gate dielectric and the second gate electrode form portions of a second FinFET, and the first FinFET and the second FinFET are of opposite conductivity types.

18 . A method comprising:
depositing a first dielectric liner extending into a first trench in a semiconductor substrate, wherein the first dielectric liner applies a first type of stress to a first semiconductor strip, with a sidewall of the first semiconductor strip facing the first trench; depositing a second dielectric liner extending into a second trench in the semiconductor substrate, wherein the second dielectric liner applies a second type of stress different from the first type of stress to a second semiconductor strip, with a sidewall of the second semiconductor strip facing the second trench; and filling a dielectric material into the first trench and the second trench to form a first isolation region and a second isolation region, respectively.

19 . The method of claim 18 , wherein the first type of stress is a tensile stress, and the second type of stress is a compressive stress.

20 . The method of claim 18 , wherein the first dielectric liner and the second dielectric liner are deposited in different deposition processes.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Tsung-Lin
• Yeh Chih Chieh
• Yuan Feng
• Chiang Hung-Li
• Lai Wei-Jen

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6538

  by exposure to UV light · CPC title

• H10P14/6529

  by exposure to a gas or vapour · CPC title