Method for forming different types of devices

Patent metadata

Field	Value
Publication number	US-12501601-B2
Application number	US-202418587506-A
Country	US
Kind code	B2
Filing date	Feb 26, 2024
Priority date	Jun 8, 2020
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; and a first transistor in a first device area of the substrate and comprising:
a fin element comprising first semiconductor layers interleaved by second semiconductor layers, and
a first gate structure wrapping over a top surface and sidewalls of the fin element,
wherein the first gate structure does not extend between any two of the first semiconductor layers and the second semiconductor layers.

2 . The semiconductor device of claim 1 , wherein sidewalls of the fin element taper upward.

3 . The semiconductor device of claim 1 ,
wherein the fin element further comprises a first base portion rising continuously from the substrate, wherein the first semiconductor layers and the second semiconductor layers are disposed over the first base portion.

4 . The semiconductor device of claim 1 , further comprising:
a second transistor in a second device area of the substrate and comprising:
a plurality of vertically stacked nanostructures, and
a second gate structure wrapping around each of the plurality of vertically stacked nanostructures.

5 . The semiconductor device of claim 4 , wherein the plurality of vertically stacked nanostructures are disposed over a second base portion rising continuously from the substrate.

6 . The semiconductor device of claim 4 , wherein a width of a bottommost one of the plurality of vertically stacked nanostructures is greater than a width of a topmost one of the plurality of vertically stacked nanostructures.

7 . The semiconductor device of claim 4 ,
wherein the first semiconductor layers and the plurality of vertically stacked nanostructures comprise silicon (Si), wherein the second semiconductor layers comprise silicon germanium (SiGe).

8 . The semiconductor device of claim 4 , wherein the second transistor further comprises:
a plurality of inner spacer features interleaving the plurality of vertically stacked nanostructures.

9 . A semiconductor structure, comprising:
a substrate; and a first transistor in a first device area of the substrate and comprising:
a fin element extending between a first source/drain feature and a second source/drain feature, and
a first gate structure wrapping over a top surface and sidewalls of the fin element,
wherein the fin element comprises first semiconductor layers interleaved by second semiconductor layers, wherein the first source/drain feature and the second source/drain feature are in direct contact with the first semiconductor layers and the second semiconductor layers, wherein a width of a topmost one of the first semiconductor layers is smaller than a width of a bottommost one of the second semiconductor layers.

10 . The semiconductor structure of claim 9 , wherein the first gate structure does not extend between any two of the first semiconductor layers and the second semiconductor layers.

11 . The semiconductor structure of claim 9 ,
wherein the first semiconductor layers comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or indium arsenide (InAs), wherein the second semiconductor layers comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn).

12 . The semiconductor structure of claim 9 , further comprising:
a second transistor in a second device area of the substrate and comprising:
a plurality of vertically stacked nanostructures extending between a third source/drain feature and a fourth source/drain feature, and
a second gate structure wrapping around each of the plurality of vertically stacked nanostructures.

13 . The semiconductor structure of claim 12 , wherein the second transistor further comprises:
a plurality of inner spacer features interleaving the plurality of vertically stacked nanostructures.

14 . The semiconductor structure of claim 13 , wherein the second gate structure is spaced apart from the third source/drain feature and the fourth source/drain feature by the plurality of inner spacer features.

15 . The semiconductor structure of claim 12 , wherein the first device area is a logic device area and the second device area is an input/output device area.

16 . The semiconductor structure of claim 12 ,
wherein the first transistor comprises a first threshold voltage, wherein the second transistor comprises a second threshold voltage different from the first threshold voltage.

17 . A semiconductor device, comprising:
a substrate; and a p-type transistor disposed over the substrate and comprising:
a fin element extending between a first p-type source/drain feature and a second p-type source/drain feature, and
a first gate structure wrapping over a top surface and sidewalls of the fin element,
wherein the fin element comprises first semiconductor layers interleaved by second semiconductor layers, wherein the first p-type source/drain feature and the second p-type source/drain feature are in direct contact with the first semiconductor layers and the second semiconductor layers, wherein the first gate structure does not extend between any two of the first semiconductor layers and the second semiconductor layers.

18 . The semiconductor device of claim 17 ,
wherein the first semiconductor layers comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), or indium arsenide (InAs), wherein the second semiconductor layers comprise silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn).

19 . The semiconductor device of claim 17 , further comprising:
an n-type transistor disposed over the substrate and comprising:
a plurality of vertically stacked nanostructures extending between a first n-type source/drain feature and a second n-type source/drain feature, and
a second gate structure wrapping around each of the plurality of vertically stacked nanostructures.

20 . The semiconductor device of claim 17 , wherein sidewalls of the fin element taper upward.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Feng-Ching
• Lee Wei-Yang
• Yang Feng-Cheng
• Chen Yen-Ming

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title