Semiconductor device

US2017170331A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017170331-A1
Application numberUS-201615238059-A
CountryUS
Kind codeA1
Filing dateAug 16, 2016
Priority dateDec 9, 2015
Publication dateJun 15, 2017
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively comprising source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other, wherein a channel region of the second transistor and a channel region of the third transistor respectively comprise a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively, and wherein a width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction. 2 . The semiconductor device of claim 1 , wherein a threshold voltage of the second transistor is greater than a threshold voltage of the third transistor. 3 . The semiconductor device of claim 2 , wherein a channel region of the first transistor comprises a plurality of channel portions that are spaced apart from each other in the second direction and are connected to the source and drain regions, respectively, and wherein the width of the channel portion of the second transistor in the first direction is greater than a width of the channel portion of the first transistor in the first direction. 4 . The semiconductor device of claim 2 , wherein a threshold voltage of the first transistor is greater than the threshold voltage of the second transistor. 5 . The semiconductor device of claim 2 , wherein the channel region of the first transistor has a shape of a fin protruding from the upper surface of the substrate. 6 . The semiconductor device of claim 2 , wherein a threshold voltage of the first transistor is less than the threshold voltage of the third transistor. 7 . The semiconductor device of claim 1 , wherein the first to third transistors have the same conductivity type. 8 . The semiconductor device of claim 1 , wherein a length of the channel portion of the third transistor in a third direction is equal to a length of the channel portion of the second transistor in the third direction, the third direction crossing the first direction on the substrate. 9 . The semiconductor device of claim 1 , wherein the plurality of channel portions of the second transistor have the same thickness. 10 . The semiconductor device of claim 1 , wherein a thickness of the channel portion of the second transistor is equal to a thickness of the channel portion of the third transistor. 11 . The semiconductor device of claim 1 , wherein a number of the plurality of channel portions of the second transistor is equal to a number of the plurality of channel portions of the third transistor. 12 . The semiconductor device of claim 1 , wherein the gate structure of one of the first to third transistors comprises a first gate electrode, a second gate electrode and a third gate electrode, and work functions of the first to third gate electrodes are equal to each other. 13 . A semiconductor device comprising: a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively comprising source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other, wherein the channel region of the first transistor has a shape of a fin protruding from an upper surface of the substrate, and wherein a channel region of the second transistor and a channel region of the third transistor respectively comprise a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to the upper surface of the substrate, and connected to the source and drain regions, respectively. 14 . The semiconductor device of claim 13 , wherein a threshold voltage of the first transistor is less than a threshold voltage of the second transistor. 15 . The semiconductor device of claim 13 , wherein a width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction. 16 . The semiconductor device of claim 15 , wherein a threshold voltage of the third transistor is less than a threshold voltage of the second transistor. 17 . The semiconductor device of claim 13 , wherein the second and third transistors comprise a second gate electrode and a third gate electrode, respectively, and wherein a work function of the third gate electrode is greater than a work function of the second gate electrode. 18 . The semiconductor device of claim 17 , wherein a threshold voltage of the second transistor is greater than a threshold voltage of the third transistor. 19 . The semiconductor device of claim 13 , wherein the first to third transistors have the same conductivity type. 20 . The semiconductor device of claim 13 , wherein a length of a channel portion of the third transistor in a third direction is equal to a length of a channel portion of the second transistor in the third direction, the third direction crossing the first direction on the substrate.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2017170331A1 cover?
A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and dra…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L29/78696. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 15 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).