Semiconductor structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12464774-B2
Application number	US-202217678288-A
Country	US
Kind code	B2
Filing date	Feb 23, 2022
Priority date	Feb 23, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a substrate; a first source/drain feature and a second source/drain feature over the substrate; semiconductor layers vertically stacked over each other, wherein the semiconductor layers connect the first source/drain feature to the second source/drain feature; a gate structure wrapping around the semiconductor layers, wherein the gate structure comprises a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer; a contact etch stop layer over the first source/drain feature and the second source/drain feature; and a seal layer over the gate structure and on sidewalls of the contact etch stop layer, wherein voids are formed between the seal layer and the semiconductor layers, wherein a portion of the voids is sandwiched between a bottom surface of the gate electrode and a top surface of the semiconductor layers.

2 . The semiconductor structure of claim 1 , wherein a width of the gate dielectric layer over the semiconductor layers is smaller than a width of the gate electrode.

3 . A semiconductor structure, comprising:
a substrate; semiconductor layers over the substrate; a gate structure wrapping around the semiconductor layers, wherein the gate structure comprises a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer; a source/drain feature in contact with the semiconductor layers; a contact etch stop layer over the source/drain feature, wherein the contact etch stop layer is separated from the gate structure by an air spacer, wherein a topmost width of the air spacer is different from a bottommost width of the air spacer, wherein a portion of the air spacer is vertically overlapped with the gate structure; and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer.

4 . The semiconductor structure of claim 3 , wherein the seal layer extends between the gate electrode and the contact etch stop layer.

5 . The semiconductor structure of claim 3 , wherein a bottommost surface of the seal layer is aligned with a top surface of the gate electrode.

6 . The semiconductor structure of claim 3 , wherein the air spacer extends between the gate electrode and a topmost surface of the semiconductor layers.

7 . The semiconductor structure of claim 3 , wherein the gate electrode has a trapezoidal top portion.

8 . A semiconductor structure, comprising:
a substrate; semiconductor layers over the substrate; source/drain features in contact with the semiconductor layers; a gate structure wrapping around the semiconductor layers, wherein the gate structure comprises a gate dielectric layer and a gate electrode, wherein a width of a topmost surface of the gate electrode is greater than a width of an interface between a bottom surface of the gate electrode and a topmost surface of the gate dielectric layer; a contact etch stop layer over the source/drain features; a seal layer over the gate structure and on sidewalls of the contact etch stop layer; and voids between the seal layer and the semiconductor layers and between the gate structure and the contact etch stop layer, wherein the voids partially expose sidewalls of the source/drain features.

9 . The semiconductor structure of claim 8 , wherein the seal layer extends between the gate structure and the contact etch stop layer.

10 . The semiconductor structure of claim 8 , wherein
the gate dielectric layer wrapping around the semiconductor layers, wherein the gate electrode wrapping around the gate dielectric layer, and the gate electrode has a trapezoidal top portion in contact with the seal layer.

11 . The semiconductor structure of claim 8 , wherein top surfaces of the voids are aligned with a top surface of the gate structure.

12 . The semiconductor structure of claim 1 , wherein the voids are in contact with the bottom surface of the gate electrode.

13 . The semiconductor structure of claim 3 , wherein the topmost width of the air spacer is greater than the bottommost width of the air spacer.

14 . The semiconductor structure of claim 3 , wherein the topmost width of the air spacer is less than the bottommost width of the air spacer.

15 . The semiconductor structure of claim 3 , wherein the portion of the air spacer exposes a portion of a bottom surface of the gate electrode.

16 . The semiconductor structure of claim 3 , wherein the portion of the air spacer is wrapped by a bottom surface of the gate electrode, a sidewall of the gate dielectric layer and a top surface of the semiconductor layers.

17 . The semiconductor structure of claim 3 , wherein the air spacer has a L-shape profile.

18 . The semiconductor structure of claim 3 , wherein the portion of the air spacer is sandwiched between a bottom surface of the gate electrode and a top surface of the semiconductor layers.

19 . The semiconductor structure of claim 3 , wherein a width of a bottom surface of the gate electrode is greater than a width of an interface between the bottom surface of the gate electrode and a topmost surface of the gate dielectric layer.

20 . The semiconductor structure of claim 3 , wherein a width of a topmost surface of the gate electrode is greater than a width of an interface between a bottom surface of the gate electrode and a topmost surface of the gate dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Lin Shih-Che
• Huang Po-Yu
• Wu Shih-Chieh
• Wu I-Wen
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title