Vertical gate all around (VGAA) devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9536738-B2
Application number	US-201514640726-A
Country	US
Kind code	B2
Filing date	Mar 6, 2015
Priority date	Feb 13, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer.

First claim

What is claimed is:

1. A method comprising:
forming a first doped region having a first conductivity in a substrate;
forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region;
patterning the first doped region to form first protrusions and patterning the second doped region to form second protrusions; and
oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer.

2. The method of claim 1 , wherein the first doped region comprises N-type dopants and the second doped region comprises P-type dopants.

3. The method of claim 1 , wherein the semiconductive layer is further disposed between the substrate and the first doped region.

4. The method of claim 1 , wherein the oxidizing the semiconductive layer comprises exposing at least a portion of the semiconductive layer to an oxygen-containing ambient environment.

5. The method of claim 1 , wherein the oxidizing the semiconductive layer comprises exposing at least a portion of the semiconductive layer to an oxygen-containing plasma.

6. The method of claim 1 , wherein the oxidizing the semiconductive layer comprises exposing at least a portion of the semiconductive layer to an annealing process.

7. The method of claim 6 , wherein the annealing process comprises an oxygen anneal or a steam anneal.

8. The method of claim 1 , wherein the first protrusions and the second protrusions comprise channel regions of a first vertical gate all around device and a second vertical gate all around device, respectively.

9. The method of claim 1 , wherein the first protrusions and the second protrusions comprise nanowires, bars, or a combination thereof.

10. The method of claim 1 further comprising forming a recess between the first doped region and the second doped region.

11. A method, comprising:
forming a first opening in a substrate;
filling the first opening with a first semiconductor material having a first conductivity type;
forming a second opening laterally adjacent to the first semiconductor material, wherein a bottom surface of the second opening is lined with a semiconductive layer;
filling the second opening with a second semiconductor material having a second conductivity type different from the first conductivity type, the second semiconductor material overlying the semiconductive layer;
forming a recess between the first semiconductor material and the second semiconductor material, the recess exposing an edge region of the semiconductive layer; and
oxidizing the semiconductive layer having the exposed edge region to form an oxidized isolation layer.

12. The method of claim 11 , wherein the semiconductive layer comprises silicon-germanium, with germanium having a concentration greater than or equal to about 20%.

13. The method of claim 11 , wherein the filling the first opening with the first semiconductor material and the filling the second opening with the second semiconductor material comprises an epitaxy process.

14. The method of claim 11 , wherein the semiconductive layer is formed on the bottom surface of the second opening using an epitaxy process.

15. The method of claim 11 , wherein the semiconductive layer further lines a bottom surface of the first opening, and wherein the filling the first opening with the first semiconductor material comprises forming the first semiconductor material over the semiconductive layer.

16. The method of claim 11 , wherein the semiconductive layer has a thickness of at least 1 nanometer.

17. A vertical gate all around device, comprising:
a semiconductor substrate;
a first doped region over the semiconductor substrate and comprising first protrusions;
a second doped region over the semiconductor substrate and comprising second protrusions, the second doped region disposed laterally adjacent to and spaced apart from the first doped region;
an oxidized isolation layer disposed between the second doped region and the semiconductor substrate; and
a first gate stack disposed around the first protrusions and a second gate stack disposed around the second protrusions.

18. The device of claim 17 , wherein the oxidized isolation layer comprises silicon, germanium, and oxygen.

19. The device of claim 17 , further comprising an isolation feature disposed between the first doped region and the second doped region.

20. The device of claim 19 , wherein a thickness of an edge region of the oxidized isolation layer proximal the isolation feature is greater than a thickness of a central region of the oxidized isolation layer distal the isolation feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien
• Lin Chun-Hsiung
• Liu Chi-Wen

Classifications

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title