Semiconductor package

Patent metadata

Field	Value
Publication number	US-12438133-B2
Application number	US-202217722616-A
Country	US
Kind code	B2
Filing date	Apr 18, 2022
Priority date	Aug 18, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate;
a connection substrate on the package substrate and an opening that penetrates the connection substrate;
a chip stack on the package substrate and in the opening of the connection substrate;
a redistribution layer on the connection substrate and the chip stack;
an upper semiconductor chip on first redistribution pads of the redistribution layer; and
a plurality of external terminals on a bottom surface of the package substrate,
wherein the chip stack includes
a first semiconductor chip on substrate pads of the package substrate; and
a second semiconductor chip on the first semiconductor chip and on second redistribution pads of the redistribution layer,

wherein the redistribution layer includes
a first region that overlaps the upper semiconductor chip; and
a second region beside of the upper semiconductor chip,

wherein the first redistribution pads are on the first region, and
wherein the second redistribution pads are on the second region and entirely outside of the first region.

2. The semiconductor package of claim 1 , wherein
the upper semiconductor chip has a width less than a width of the second semiconductor chip,
the upper semiconductor chip is within a perimeter of the second semiconductor chip, and
the second region surrounds the first region.

3. The semiconductor package of claim 1 , wherein
the upper semiconductor chip runs across the second semiconductor chip in a first direction parallel to a top surface of the redistribution layer, and
the second region is on at least one side of the first region in a second direction that intersects the first direction.

4. The semiconductor package of claim 1 , wherein
the upper semiconductor chip is offset from the second semiconductor chip in a first direction parallel to a top surface of the redistribution layer, and
the first region is in the first direction from the second region.

5. The semiconductor package of claim 1 , wherein
at least one of the first redistribution pads overlap the second semiconductor chip, and
the second redistribution pads do not overlap the upper semiconductor chip.

6. The semiconductor package of claim 1 , wherein
the upper semiconductor chip includes a first active surface that faces the redistribution layer, and first chip terminals of the upper semiconductor chip are connected to the first redistribution pads between the upper semiconductor chip and the redistribution layer, and
the second semiconductor chip includes a second active surface that faces the redistribution layer, and second chip terminals of the second semiconductor chip are connected to the second redistribution pads between the second semiconductor chip and the redistribution layer.

7. The semiconductor package of claim 1 , wherein the redistribution layer includes:
a dielectric pattern;
the first redistribution pads and the second redistribution pads on a top surface of the dielectric pattern; and
a protection layer on the top surface of the dielectric pattern, the protection layer that covers the first redistribution pads and the second redistribution pads.

8. The semiconductor package of claim 1 , wherein the redistribution layer includes:
a dielectric pattern;
the first redistribution pads and the second redistribution pads that are on a top surface of the dielectric pattern;
a protection layer on a top surface of the dielectric pattern and that covers the first redistribution pads and the second redistribution pads; and
a third redistribution pad on the protection layer and connected through a vertical connection via to the first redistribution pad,
wherein upper chip terminal of the upper semiconductor chip is directly connected to the third redistribution pad, and
wherein a second chip terminal of the second semiconductor chip penetrates the dielectric pattern to be directly connected to the second redistribution pad.

9. The semiconductor package of claim 1 , wherein
the upper semiconductor chip is provided in plural, and
the second region of the redistribution layer is between the plurality of upper semiconductor chips.

10. A semiconductor package, comprising:
a package substrate;
a first semiconductor chip on the package substrate;
a redistribution layer on the first semiconductor chip;
a second semiconductor chip mounted on a first surface of the redistribution layer;
a third semiconductor chip mounted on a second surface of the redistribution layer; and
a connection member between the package substrate and the redistribution layer and beside of the first semiconductor chip, the connection member connects the package substrate to the redistribution layer,
wherein the redistribution layer includes a first redistribution pad and a second redistribution pad that are at a same level from the package substrate,
wherein the second semiconductor chip is directly connected through a first terminal on the first redistribution pad,
wherein the third semiconductor chip is directly connected through a second terminal on the second redistribution pad,
wherein the redistribution layer includes a first region on which the first redistribution pad is provided and a second region on which the second redistribution pad is provided,
wherein the second redistribution pad vertically overlaps both of the second semiconductor chip and the third semiconductor chip, and
wherein the first region vertically overlaps the second semiconductor chip and is laterally spaced apart from the third semiconductor chip.

11. The semiconductor package of claim 10 , wherein
the first surface of the redistribution layer is directed toward the package substrate, and
an inactive surface of the second semiconductor chip is in contact with an inactive surface of the first semiconductor chip.

12. The semiconductor package of claim 10 , wherein
the third semiconductor chip has a width less than a width of the second semiconductor chip, and the third semiconductor chip is within a perimeter of the second semiconductor chip, and
the first region surrounds the second region.

13. The semiconductor package of claim 10 , wherein the redistribution layer includes:
a dielectric pattern;
the first redistribution pad and the second redistribution pad that are on a top surface of the dielectric pattern; and
a protection layer on the top surface of the dielectric pattern, the protection layer covers the first redistribution pad and the second redistribution pad.

14. The semiconductor package of claim 10 , further comprising a dielectric layer that fills a space between the package substrate and the redistribution layer,
wherein the connection member includes a through electrode that vertically penetrates the dielectric layer.

15. The semiconductor package of claim 10 , further comprising:
a connection substrate between the package substrate and the redistribution layer and having an opening that penetrates the connection substrate, the first semiconductor chip and the second semiconductor chip being in the opening; and
a dielectric layer that fills a space between the connection substrate and the first and second semiconductor chips in the opening,
wherein the connection member includes a substrate wiring pattern in the connection substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Joonsung

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title