Electronic device package

Patent metadata

Field	Value
Publication number	US-9859255-B1
Application number	US-201615283342-A
Country	US
Kind code	B1
Filing date	Oct 1, 2016
Priority date	Oct 1, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a package substrate, an electronic component, a mold compound encapsulating the electronic component, and a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer. The redistribution layer and the package substrate can be electrically coupled. In addition, the redistribution layer and the electronic component can be electrically coupled to electrically couple the electronic component and the package substrate. Associated systems and methods are also disclosed.

First claim

What is claimed is:

1. An electronic device package, comprising:
a package substrate;
first and second electronic components in a stacked relationship, the second component electrically coupled to the package substrate by a wire bond connection;
a mold compound encapsulating the first and second electronic components;
a spacer comprising a film over wire (FOW) separating the first and second electronic components to provide clearance for the wire bond connection; and
a redistribution layer disposed such that the mold compound is between the package substrate and the redistribution layer, wherein the redistribution layer and the package substrate are electrically coupled, and the redistribution layer and the first electronic component are electrically coupled to electrically couple the first electronic component and the package substrate.

2. The electronic device package of claim 1 , wherein the redistribution layer and the first electronic component are electrically coupled by a conductive pillar.

3. The electronic device package of claim 1 , wherein the redistribution layer and the first electronic component are electrically coupled by a wire bond connection.

4. The electronic device package of claim 1 , wherein the redistribution layer is configured to facilitate electrically coupling the electronic device package with an external electronic component.

5. The electronic device package of claim 1 , wherein the mold compound comprises an epoxy.

6. The electronic device package of claim 1 , wherein the second electronic component comprises an integrated circuit.

7. The electronic device package of claim 1 , further comprising a third electronic component electrically coupled to the package substrate.

8. The electronic device package of claim 1 , further comprising a fourth electronic component electrically coupled to the package substrate.

9. A computing system, comprising:
a motherboard; and
an electronic device package as recited in claim 1 , operably coupled to the motherboard.

10. The electronic device package of claim 2 , wherein the conductive pillar comprises a metal material.

11. The electronic device package of claim 10 , wherein the metal material comprises copper.

12. The electronic device package of claim 3 , wherein the wire bond connection comprises a vertical wire bond connection.

13. The electronic device package of claim 4 , further comprising a plurality of solder balls coupled to the redistribution layer to facilitate electrically coupling the electronic device package with the external electronic component.

14. The electronic device package of claim 6 , wherein the integrated circuit comprises an application specific integrated circuit.

15. The electronic device package of claim 6 , wherein the first electronic component comprises computer memory.

16. The electronic device package of claim 7 , wherein the third electronic component is disposed on a side of the package substrate opposite the first electronic component.

17. The electronic device package of claim 7 , wherein the third electronic component is electrically coupled to the package substrate with either solder balls or a wire bond connection.

18. The electronic device package of claim 17 , wherein the third electronic component is electrically coupled to the package substrate with solder balls.

19. The electronic device package of claim 8 , wherein the fourth electronic component is disposed on a side of the package substrate opposite the first electronic component.

20. The electronic device package of claim 8 , wherein the fourth electronic component is electrically coupled to the package substrate with either solder balls or a wire bond connection.

21. The system of claim 8 , wherein the computing system comprises a desktop computer, a laptop, a tablet, a smartphone, a server, a wearable electronic device, or a combination thereof.

22. The system of claim 8 , further comprising a processor, a memory device, a heat sink, a radio, a slot, a port, or a combination thereof operably coupled to the motherboard.

23. The electronic device package of claim 20 , wherein the fourth electronic component is electrically coupled to the package substrate with a wire bond connection.

Assignees

• Intel Corp

Inventors

• Yoon Jh
• She Yong
• Guo Mao
• Patten Richard

Classifications

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/231

  the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W72/834

  Interconnections on sidewalls of chips · CPC title