Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10854551-B2
Application number	US-201816161460-A
Country	US
Kind code	B2
Filing date	Oct 16, 2018
Priority date	Feb 6, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads and a plurality of second redistribution pads on the first surface, the plurality of second redistribution pads having a pitch different from a pitch of the plurality of first redistribution pads;
a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer;
a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip; and
a plurality of external connection terminals on and coupled to the conductive structures, the plurality of external connection terminals having a non-overlapping relationship with respect to the semiconductor chip, in a top view, and the pitch of the plurality of first redistribution pads being smaller than a pitch of the plurality of external connection terminals.

2. The package as claimed in claim 1 , wherein the semiconductor chip includes a programmable chip.

3. The package as claimed in claim 1 , wherein the plurality of second redistribution pads overlaps a different area of the redistribution layer than the plurality of first redistribution pads, as viewed in the top view.

4. The package as claimed in claim 1 , wherein, when viewed in a plan view, at least one of the plurality of first redistribution pads is spaced apart from the semiconductor chip.

5. The package as claimed in claim 1 , further comprising a first semiconductor device on the first surface of the redistribution layer, the first semiconductor device being coupled to the plurality of first redistribution pads.

6. The package as claimed in claim 1 , wherein at least some of the plurality of first redistribution pads are coupled to the external connection terminals through the redistribution layer and the conductive structures.

7. The package as claimed in claim 1 , further comprising a plurality of base layers on the redistribution layer, a hole penetrating the plurality of base layers, and the semiconductor chip being inside the hole.

8. The package as claimed in claim 1 , wherein the plurality of external connection terminals is arranged around a perimeter of the semiconductor chip and horizontally spaced apart from the semiconductor chip.

9. The package as claimed in claim 1 , wherein the plurality of first redistribution pads and the semiconductor chip have a non-overlapping relationship.

10. The package as claimed in claim 1 , wherein the redistribution layer includes:
an insulation pattern; and
a redistribution pattern in the insulation pattern, the plurality of first redistribution pads being coupled to the redistribution pattern.

11. A semiconductor package, comprising:
a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface;
a plurality of base layers on the second surface of the redistribution layer, a hole penetrating the plurality of base layers;
a semiconductor chip inside the hole on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer;
a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip;
a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals,
wherein at least one of the conductive structures includes:
a first pad on an uppermost one of the plurality of base layers;
a conductive pattern between two base layers of the plurality of base layers;
a via penetrating each one of the plurality of base layers, the via being coupled to the conductive pattern; and
a second pad on a lowermost one of the plurality of base layers, the second pad being horizontally offset with respect to the first pad.

12. A semiconductor package, comprising:
a redistribution layer having a first surface and a second surface opposite to each other;
a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including a chip pad facing the redistribution layer;
a plurality of conductive structures on the second surface of the redistribution layer and spaced apart from the semiconductor chip;
a first semiconductor device including a first semiconductor chip on the first surface of the redistribution layer, the first semiconductor device including Hail at least three connection pads facing the redistribution layer; and
a plurality of first redistribution pads on the first surface of the redistribution layer, the plurality of first redistribution pads being connected to the connection pads, respectively, and the plurality of first redistribution pads having a non-vertically overlapping relationship with the semiconductor chip.

13. The package as claimed in claim 12 , further comprising a second semiconductor device on the first surface of the redistribution layer, the second semiconductor device having a height different from a height of the first semiconductor device.

14. The package as claimed in claim 12 , wherein, when viewed in a plan view, at least a portion of the first semiconductor device does not overlap the semiconductor chip.

15. The package as claimed in claim 12 , wherein the first semiconductor device further includes:
a package substrate,
the first semiconductor chip on the package substrate; and
a molding member on the package substrate and covering the first semiconductor chip.

16. The package as claimed in claim 12 , wherein the first semiconductor device and the semiconductor chip are on opposite surfaces of the redistribution layer, the first semiconductor device and the semiconductor chip being connected to each other via the redistribution layer and the plurality of first redistribution pads on the first surface of the redistribution layer, and all the plurality of first redistribution pads being in a region overlapped by the first semiconductor device.

17. The package as claimed in claim 12 , further comprising a molding pattern on the second surface of the redistribution layer and covering the semiconductor chip, the molding pattern being between the semiconductor chip and the conductive structures.

18. The package as claimed in claim 17 , further comprising:
a lower redistribution layer on a lower surface of the molding pattern, the lower redistribution layer being coupled to the conductive structures; and
a plurality of external connection terminals on a lower surface of the lower redistribution layer, the plurality of external connection terminals being coupled to the lower redistribution layer and to the conductive structures.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Hae-Jung
• Oh Kyung Suk

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title